drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1093

value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CONTROL,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1187

value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1197

value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_RG,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1202

value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC0_DATA_B,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1207

value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC1_DATA_RG,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1212

value = dm_read_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC1_DATA_B,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

173

uint32_t value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

189

uint32_t value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

200

value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

251

dm_read_reg_soc15(tg->ctx,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

313

uint32_t pol_value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

375

uint32_t value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

417

value = dm_read_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

514

value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

603

uint32_t v_blank_start_end = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

631

uint32_t value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

672

value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

720

uint32_t value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

90

uint32_t value = dm_read_reg_soc15(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1057

uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

678

uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

687

reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1336

uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);