drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

446

struct dpu_sw_pipe_cfg *cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

199

struct dpu_sw_pipe_cfg *cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

357

static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c

194

struct dpu_sw_pipe_cfg *cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1011

static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1012

struct dpu_sw_pipe *r_pipe, struct dpu_sw_pipe_cfg *r_pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1047

struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1114

struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1115

struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

119

struct dpu_sw_pipe_cfg *pipe_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1201

struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1210

struct dpu_sw_pipe_cfg *r_pipe_cfg = pipe_cfg + 1;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1251

struct dpu_sw_pipe_cfg *pipe_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1404

struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1646

const struct dpu_sw_pipe_cfg *pipe_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

166

struct dpu_sw_pipe_cfg *pipe_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

255

const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

362

struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

533

struct dpu_sw_pipe_cfg *pipe_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

584

struct dpu_sw_pipe_cfg pipe_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

728

struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

827

struct dpu_sw_pipe_cfg *pipe_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

828

struct dpu_sw_pipe_cfg *r_pipe_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

919

struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

942

static int dpu_plane_is_parallel_capable(struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

954

struct dpu_sw_pipe_cfg *pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

964

struct dpu_sw_pipe_cfg **single_pipe_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

990

struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

991

struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->pipe_cfg[1];

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

35

struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];