drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h

18

struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h

22

struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h

28

struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h

31

void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

115

static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

179

struct dpu_kms *kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

220

static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

263

struct dpu_kms *kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

285

static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

323

struct dpu_kms *kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

465

int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent)

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

467

struct dpu_core_perf *perf = &dpu_kms->perf;

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

72

struct dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

74

int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1048

struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1067

dpu_vbif_clear_errors(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1091

struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1124

dpu_vbif_clear_errors(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1374

struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1413

else if (dpu_kms->catalog->caps->has_3d_merge)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1431

struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1449

topology = dpu_crtc_get_topology(crtc, dpu_kms, crtc_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1450

ret = dpu_rm_reserve(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1457

num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1461

num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1465

num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1592

struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1598

if (!dpu_kms->catalog->caps->has_3d_merge &&

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1599

mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1603

dpu_kms->perf.perf_cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1605

if (dpu_kms->catalog->caps->has_3d_merge)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1612

if (dpu_kms->perf.max_core_clk_rate < adjusted_mode_clk * 1000)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1619

2 * dpu_kms->catalog->caps->max_mixer_width,

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1861

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1894

if (dpu_kms->catalog->dspp_count) {

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1895

const struct dpu_dspp_cfg *dspp = &dpu_kms->catalog->dspp[0];

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

47

static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

771

struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

777

if (!dpu_kms->catalog->caps->has_3d_merge &&

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

778

adj_mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

790

if (drm_rect_width(r) > dpu_kms->catalog->caps->max_mixer_width)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1158

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1180

dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1184

global_state = dpu_kms_get_existing_global_state(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1194

num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1198

num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1203

num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1216

num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1223

num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1237

dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2191

global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2193

num_lm = dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2356

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2372

dpu_kms = phys_enc->dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2373

global_state = dpu_kms_get_existing_global_state(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2374

num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2629

struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2644

phys_params.dpu_kms = dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2654

dpu_kms->catalog->caps->has_idle_pc;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2677

phys_params.hw_intf = dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms->rm,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2682

phys_params.hw_wb = dpu_rm_get_wb(&dpu_kms->rm, controller_id);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2697

ret = dpu_encoder_virt_add_phys_encs(dpu_kms->dev, disp_info,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2763

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2779

ret = dpu_encoder_setup_display(dpu_enc, dpu_kms, disp_info);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2931

phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2935

phys_enc->dpu_kms = p->dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

500

irq_status = dpu_core_irq_read(phys_enc->dpu_kms, irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

664

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

689

if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

760

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

781

dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

782

hw_mdptop = dpu_kms->hw_mdp;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

852

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

857

dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

867

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

876

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

881

dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

894

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

185

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

262

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

203

dpu_core_irq_unregister_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

272

ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

280

ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

304

dpu_core_irq_register_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

308

dpu_core_irq_register_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

315

dpu_core_irq_register_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

328

dpu_core_irq_unregister_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

331

dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

333

dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

345

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

364

dpu_kms = phys_enc->dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

375

vsync_hz = dpu_kms_get_clk_rate(dpu_kms, "vsync");

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

72

if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

764

if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

299

fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

380

return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) &&

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

419

ret = dpu_core_irq_register_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

427

ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

453

fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

572

dpu_core_irq_unregister_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

681

dpu_core_irq_register_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

694

dpu_core_irq_unregister_callback(phys_enc->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

121

if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

125

dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

128

_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

143

if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

148

catalog = phys_enc->dpu_kms->catalog;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

179

if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

204

const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

231

if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

390

dpu_core_irq_register_callback(phys->dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

406

dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

554

if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

76

if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

80

dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

83

_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

305

static void dpu_core_irq_callback_handler(struct dpu_kms *dpu_kms, unsigned int irq_idx)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

307

struct dpu_hw_intr_entry *irq_entry = dpu_core_irq_get_entry(dpu_kms->hw_intr, irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

332

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

333

struct dpu_hw_intr *intr = dpu_kms->hw_intr;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

372

dpu_core_irq_callback_handler(dpu_kms, irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

499

static void dpu_clear_irqs(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

501

struct dpu_hw_intr *intr = dpu_kms->hw_intr;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

517

static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

519

struct dpu_hw_intr *intr = dpu_kms->hw_intr;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

541

u32 dpu_core_irq_read(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

544

struct dpu_hw_intr *intr = dpu_kms->hw_intr;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

635

int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

659

spin_lock_irqsave(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

661

irq_entry = dpu_core_irq_get_entry(dpu_kms->hw_intr, irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

663

spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

673

dpu_kms->hw_intr,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

678

spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

694

int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

710

spin_lock_irqsave(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

713

ret = dpu_hw_intr_disable_irq_locked(dpu_kms->hw_intr, irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

718

irq_entry = dpu_core_irq_get_entry(dpu_kms->hw_intr, irq_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

722

spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

732

struct dpu_kms *dpu_kms = s->private;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

739

spin_lock_irqsave(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

740

irq_entry = dpu_core_irq_get_entry(dpu_kms->hw_intr, i);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

743

spin_unlock_irqrestore(&dpu_kms->hw_intr->irq_lock, irq_flags);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

760

void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

763

debugfs_create_file("core_irq", 0600, parent, dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

775

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

779

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

780

dpu_clear_irqs(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

781

dpu_disable_all_irqs(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

782

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

785

irq_entry = dpu_core_irq_get_entry(dpu_kms->hw_intr, i);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

797

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

801

if (!dpu_kms->hw_intr)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

804

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

806

irq_entry = dpu_core_irq_get_entry(dpu_kms->hw_intr, i);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

812

dpu_clear_irqs(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

813

dpu_disable_all_irqs(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

814

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

663

int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

324

struct dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

332

int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1016

dpu_kms->mmio + cat->mixer[i].base,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1022

dpu_kms->mmio + cat->wb[i].base, "%s",

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1025

if (dpu_kms->catalog->mdss_ver->core_major_ver >= 8) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1027

dpu_kms->mmio + cat->mdp[0].base, "top");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1029

dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1032

dpu_kms->mmio + cat->mdp[0].base, "top");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1038

dpu_kms->mmio + cat->cwb[i].base, cat->cwb[i].name);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1042

base = dpu_kms->mmio + cat->dsc[i].base;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1059

dpu_kms->mmio + cat->cdm->base,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1062

for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1063

const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1066

dpu_kms->vbif[vbif->id] + vbif->base,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1070

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1094

static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1098

if (!dpu_kms->base.vm)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1101

mmu = to_msm_vm(dpu_kms->base.vm)->mmu;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1104

drm_gpuvm_put(dpu_kms->base.vm);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1106

dpu_kms->base.vm = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1109

static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1113

vm = msm_kms_init_vm(dpu_kms->dev, dpu_kms->dev->dev->parent);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1117

dpu_kms->base.vm = vm;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1129

unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1133

clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1144

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

115

struct dpu_kms *kms = file->private_data;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1155

dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1156

dev = dpu_kms->dev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1161

rc = dpu_kms_global_obj_init(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1165

atomic_set(&dpu_kms->bandwidth_ref, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1167

rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1171

core_rev = readl_relaxed(dpu_kms->mmio + 0x0);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1175

dpu_kms->catalog = of_device_get_match_data(dev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1176

if (!dpu_kms->catalog) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1186

rc = _dpu_kms_mmu_init(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1192

dpu_kms->mdss = qcom_ubwc_config_get_data();

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1193

if (IS_ERR(dpu_kms->mdss)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1194

rc = PTR_ERR(dpu_kms->mdss);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1199

if (!dpu_kms->mdss) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1205

rc = dpu_rm_init(dev, &dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1211

dpu_kms->hw_mdp = dpu_hw_mdptop_init(dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1212

dpu_kms->catalog->mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1213

dpu_kms->mmio,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1214

dpu_kms->catalog->mdss_ver);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1215

if (IS_ERR(dpu_kms->hw_mdp)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1216

rc = PTR_ERR(dpu_kms->hw_mdp);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1218

dpu_kms->hw_mdp = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1222

for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1224

const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1226

hw = dpu_hw_vbif_init(dev, vbif, dpu_kms->vbif[vbif->id]);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1233

dpu_kms->hw_vbif[vbif->id] = hw;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1237

max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

124

static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1243

rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1256

if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,sc8180x-dpu"))

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1257

dpu_kms->hw_mdp->ops.dp_phy_intf_sel(dpu_kms->hw_mdp, (unsigned int[]){ 1, 2, });

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1259

dpu_kms->hw_intr = dpu_hw_intr_init(dev, dpu_kms->mmio, dpu_kms->catalog);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1260

if (IS_ERR(dpu_kms->hw_intr)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1261

rc = PTR_ERR(dpu_kms->hw_intr);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1263

dpu_kms->hw_intr = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1281

rc = _dpu_kms_drm_obj_init(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1287

dpu_vbif_init_memtypes(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1289

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1294

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1296

_dpu_kms_hw_destroy(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1306

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1317

ret = msm_kms_init(&dpu_kms->base, &kms_funcs);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1322

dpu_kms->dev = ddev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1325

dpu_kms->rpm_enabled = true;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1330

static int dpu_kms_mmap_mdp5(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1332

struct platform_device *pdev = dpu_kms->pdev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1336

if (!dev_is_platform(dpu_kms->pdev->dev.parent))

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1339

mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1341

dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1342

if (IS_ERR(dpu_kms->mmio)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1343

ret = PTR_ERR(dpu_kms->mmio);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1345

dpu_kms->mmio = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1348

DRM_DEBUG("mapped dpu address space @%p\n", dpu_kms->mmio);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1350

dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1351

dpu_kms->pdev,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1353

if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1354

ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1356

dpu_kms->vbif[VBIF_RT] = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1360

dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1361

dpu_kms->pdev,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1363

if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1364

dpu_kms->vbif[VBIF_NRT] = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1371

static int dpu_kms_mmap_dpu(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1373

struct platform_device *pdev = dpu_kms->pdev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1376

dpu_kms->mmio = msm_ioremap(pdev, "mdp");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1377

if (IS_ERR(dpu_kms->mmio)) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1378

ret = PTR_ERR(dpu_kms->mmio);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1380

dpu_kms->mmio = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1383

DRM_DEBUG("mapped dpu address space @%p\n", dpu_kms->mmio);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1385

dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1386

if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1387

ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1389

dpu_kms->vbif[VBIF_RT] = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1393

dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt");

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1394

if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1395

dpu_kms->vbif[VBIF_NRT] = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1405

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1412

dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1413

if (!dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1416

dpu_kms->pdev = pdev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1426

ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1430

dpu_kms->num_clocks = ret;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1436

dpu_kms->base.irq = irq;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1438

if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5"))

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1439

ret = dpu_kms_mmap_mdp5(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1441

ret = dpu_kms_mmap_dpu(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1445

ret = dpu_kms_parse_data_bus_icc_path(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1449

return msm_drv_probe(&pdev->dev, dpu_kms_init, &dpu_kms->base);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1462

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1466

clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1468

for (i = 0; i < dpu_kms->num_paths; i++)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1469

icc_set_bw(dpu_kms->path[i], 0, 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1479

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1483

ddev = dpu_kms->dev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1485

rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

1491

dpu_vbif_init_memtypes(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

150

struct dpu_kms *kms = file->private_data;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

179

static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

185

dpu_kms, &dpu_debugfs_danger_stats_fops);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

187

dpu_kms, &dpu_debugfs_safe_stats_fops);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

189

dpu_kms, &dpu_plane_danger_enable);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

199

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

205

struct dpu_kms *dpu_kms = regset->dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

209

if (!dpu_kms->mmio)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

212

base = dpu_kms->mmio + regset->offset;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

221

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

231

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

254

uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

258

if (WARN_ON(!name || !dpu_kms || !length))

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

261

regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

268

regset->dpu_kms = dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

273

static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

282

struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

287

_dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

293

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

308

dpu_debugfs_danger_init(dpu_kms, entry);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

309

dpu_debugfs_vbif_init(dpu_kms, entry);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

310

dpu_debugfs_core_irq_init(dpu_kms, entry);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

311

dpu_debugfs_sspp_init(dpu_kms, entry);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

313

return dpu_core_perf_debugfs_init(dpu_kms, entry);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

325

dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

327

return to_dpu_global_state(dpu_kms->global_state.state);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

337

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

341

&dpu_kms->global_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

384

static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

392

drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

396

state->rm = &dpu_kms->rm;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

401

static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

403

drm_atomic_private_obj_fini(&dpu_kms->global_state);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

406

static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

410

struct device *dpu_dev = &dpu_kms->pdev->dev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

418

dpu_kms->path[0] = path0;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

419

dpu_kms->num_paths = 1;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

422

dpu_kms->path[1] = path1;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

423

dpu_kms->num_paths++;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

440

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

441

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

446

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

447

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

465

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

468

for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

479

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

484

for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

533

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

536

for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

580

struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

59

static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

650

struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

66

struct dpu_kms *kms = s->private;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

673

yuv_supported = !!dpu_kms->catalog->cdm;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

686

struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

716

struct msm_drm_private *priv, struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

732

maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

759

struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

764

rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

770

rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

776

rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

783

if (dpu_kms->catalog->wb_count) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

784

for (i = 0; i < dpu_kms->catalog->wb_count; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

785

if (dpu_kms->catalog->wb[i].id == WB_2) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

786

rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

787

dpu_kms->catalog->wb[i].format_list,

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

788

dpu_kms->catalog->wb[i].num_formats);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

801

static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

815

dev = dpu_kms->dev;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

817

catalog = dpu_kms->catalog;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

823

ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

887

static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

891

dpu_kms->hw_intr = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

894

_dpu_kms_mmu_destroy(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

896

for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

897

dpu_kms->hw_vbif[i] = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

900

dpu_kms_global_obj_fini(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

902

dpu_kms->catalog = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

904

dpu_kms->hw_mdp = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

909

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

916

dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

918

_dpu_kms_hw_destroy(dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

920

msm_kms_destroy(&dpu_kms->base);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

922

if (dpu_kms->rpm_enabled)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

923

pm_runtime_disable(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

929

struct dpu_kms *dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

931

if (!dpu_kms || !dpu_kms->dev)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

934

priv = dpu_kms->dev->dev_private;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

944

struct dpu_kms *dpu_kms;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

948

dpu_kms = to_dpu_kms(kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

950

cat = dpu_kms->catalog;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

952

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

957

dpu_kms->mmio + cat->ctl[i].base, "%s",

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

962

base = dpu_kms->mmio + cat->dspp[i].base;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

976

dpu_kms->mmio + cat->intf[i].base, "%s",

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

981

base = dpu_kms->mmio + cat->pingpong[i].base;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

996

base = dpu_kms->mmio + cat->sspp[i].base;

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

115

#define to_dpu_kms(x) container_of(x, struct dpu_kms, base)

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

139

*dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

155

uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

170

unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1111

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1117

uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1123

pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1208

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1215

pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1227

dpu_kms->catalog->caps->max_linewidth))

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1230

r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1247

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1280

dpu_kms->catalog->caps->max_linewidth,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1701

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1707

pm_runtime_get_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1713

pm_runtime_put_sync(&dpu_kms->pdev->dev);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1720

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1721

bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0) &&

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1722

(dpu_kms->mdss->ubwc_dec_version == 0);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1770

struct dpu_kms *kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1827

struct dpu_kms *kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

1868

struct dpu_kms *kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

367

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

380

if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

384

dpu_vbif_set_ot_limit(dpu_kms, &ot_params);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

387

_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

401

struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

415

if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

419

dpu_vbif_set_qos_remap(dpu_kms, &qos_params);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

422

_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

733

struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

824

struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

99

static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

14

static struct dpu_hw_vbif *dpu_get_vbif(struct dpu_kms *dpu_kms, enum dpu_vbif vbif_idx)

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

16

if (vbif_idx < ARRAY_SIZE(dpu_kms->hw_vbif))

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

168

void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

17

return dpu_kms->hw_vbif[vbif_idx];

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

175

vbif = dpu_get_vbif(dpu_kms, params->vbif_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

212

void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

224

vbif = dpu_get_vbif(dpu_kms, params->vbif_idx);

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

257

void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

262

for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

263

vbif = dpu_kms->hw_vbif[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

278

void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms)

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

283

for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

284

vbif = dpu_kms->hw_vbif[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

295

void dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

303

for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

304

const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

41

void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

44

void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms,

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

47

void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

49

void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

51

void dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

15

struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);

drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c

24

return drm_add_modes_noedid(connector, dpu_kms->catalog->caps->max_mixer_width,