drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

409

struct dpu_hw_stage_cfg *stage_cfg

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

443

struct dpu_hw_stage_cfg *stage_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

529

struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

508

enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

272

enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

226

static int _set_staged_sspp(u32 stage, struct dpu_hw_stage_cfg *stage_cfg,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

281

struct dpu_hw_stage_cfg *stage_cfg)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

14

struct dpu_hw_stage_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

66

struct dpu_hw_stage_cfg *stage_cfg);