arch/sparc/vdso/vma.c

251

struct page *dp, **dpp = NULL;

arch/sparc/vdso/vma.c

291

dpp = kzalloc_objs(struct page *, dnpages);

arch/sparc/vdso/vma.c

292

vvar_mapping.pages = dpp;

arch/sparc/vdso/vma.c

294

if (!dpp)

arch/sparc/vdso/vma.c

301

dpp[0] = dp;

arch/sparc/vdso/vma.c

319

if (dpp != NULL) {

arch/sparc/vdso/vma.c

321

if (dpp[i] != NULL)

arch/sparc/vdso/vma.c

322

__free_page(dpp[i]);

arch/sparc/vdso/vma.c

324

kfree(dpp);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9844

adev->dm.dc->caps.color.dpp.gamma_corr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1110

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1709

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1879

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c

63

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

775

has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1399

adev->dm.dc->caps.color.dpp.gamma_corr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1624

struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

170

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

325

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

326

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

327

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

332

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

293

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

294

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

295

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

300

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

317

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

567

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

568

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

569

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

574

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/core/dc.c

6773

state->dpp[i].dpp_clock_enable = (pipe_ctx->plane_res.dpp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

6780

state->dpp[i].recout_start_x = dscl_data->recout.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

6781

state->dpp[i].recout_start_y = dscl_data->recout.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

6782

state->dpp[i].recout_width = dscl_data->recout.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6783

state->dpp[i].recout_height = dscl_data->recout.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6786

state->dpp[i].mpc_width = dscl_data->mpc_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

6787

state->dpp[i].mpc_height = dscl_data->mpc_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

6790

state->dpp[i].dscl_mode = dscl_data->dscl_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

6793

state->dpp[i].horz_ratio_int = dscl_data->ratios.h_scale_ratio >> 19; // Extract integer part from programmed ratio

drivers/gpu/drm/amd/display/dc/core/dc.c

6794

state->dpp[i].vert_ratio_int = dscl_data->ratios.v_scale_ratio >> 19; // Extract integer part from programmed ratio

drivers/gpu/drm/amd/display/dc/core/dc.c

6797

state->dpp[i].h_taps = dscl_data->taps.h_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back

drivers/gpu/drm/amd/display/dc/core/dc.c

6798

state->dpp[i].v_taps = dscl_data->taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1740

struct dpp *dpp, uint32_t hw_mult)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1743

seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1948

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1954

if (dpp && dpp->funcs->dpp_setup) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1956

dpp->funcs->dpp_setup(dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1968

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1973

if (dpp->funcs->dpp_program_bias_and_scale)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1974

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2407

struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2410

if (dpp->funcs->dpp_set_hdr_multiplier)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2411

dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2820

struct dpp *dpp = params->dpp_dppclk_control_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2824

if (dpp && dpp->funcs->dpp_dppclk_control)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2825

dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2915

struct dpp *dpp = params->dpp_reset_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2917

if (dpp && dpp->funcs->dpp_reset)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2918

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3013

struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3017

if (dpp && dpp->funcs->set_cursor_matrix)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3018

dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3067

struct dpp *dpp = params->dpp_set_scaler_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3070

if (dpp && dpp->funcs->dpp_set_scaler)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3071

dpp->funcs->dpp_set_scaler(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3594

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3600

seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3732

struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3736

seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3912

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3918

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3926

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3931

seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1583

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1584

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1585

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1595

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1596

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1597

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1610

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1611

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1612

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2358

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2362

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2374

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2382

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2385

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2392

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2395

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2402

pipe->plane_res.dpp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2404

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2411

pipe->plane_res.dpp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2413

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2616

split_pipe->plane_res.dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3790

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3935

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5559

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

984

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

988

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

419

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

420

(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))

drivers/gpu/drm/amd/display/dc/dc.h

274

struct dpp_color_caps dpp;

drivers/gpu/drm/amd/display/dc/dc.h

2997

} dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

807

bool dpp: 1;

drivers/gpu/drm/amd/display/dc/dc.h

827

bool dpp : 1; /* Display pipes and planes */

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1068

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1077

pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1083

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1093

pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1138

pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1148

pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1199

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

372

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

398

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

343

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

153

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

343

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

346

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

353

dpp->inst, s.igam_input_format,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

318

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

540

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1891

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

471

} dpp;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13150

out->informative.dpp.total_num_dpps_required = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13153

out->informative.dpp.total_num_dpps_required += mode_lib->mp.NoOfDPP[k];

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

125

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

131

dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

137

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

138

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

174

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

188

void dpp_reset(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

190

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

192

dpp->filter_h_c = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

193

dpp->filter_v_c = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

194

dpp->filter_h = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

195

dpp->filter_v = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

200

memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

201

memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

209

struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

211

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

225

re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

226

if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

230

dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

232

if (dpp->is_write_to_ram_a_safe)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

239

dpp->pwl_data = *params;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

241

re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

242

dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

265

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

268

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

280

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

293

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

416

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

42

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

420

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

437

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

443

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

45

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

49

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

498

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

501

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

515

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

519

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

522

if (dpp->tf_mask->DPPCLK_RATE_CONTROL)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

532

void dpp_force_disable_cursor(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

534

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

582

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

589

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

591

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

592

dpp->base.funcs = &dcn10_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

593

dpp->base.caps = &dcn10_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

595

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

596

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

597

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

599

dpp->lb_pixel_depth_supported =

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

605

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

606

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

94

void dpp_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

97

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1360

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1385

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1389

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1396

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1411

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1415

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1419

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1423

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1429

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1433

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1439

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1443

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1446

void dpp1_full_bypass(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1449

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1452

void dpp1_set_degamma_pwl(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1455

void dpp_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1458

void dpp_reset(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1461

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1466

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1470

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1475

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1480

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1483

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1487

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1491

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1495

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1499

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1507

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1512

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1516

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1527

void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1529

void dpp_force_disable_cursor(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

30

#define TO_DCN10_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

31

container_of(dpp, struct dcn10_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

118

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

119

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

120

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

121

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

129

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

139

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

149

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

161

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

164

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

169

program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

180

program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

184

static void read_gamut_remap(struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

196

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

197

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

198

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

199

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

207

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

217

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

227

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

233

void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

236

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

240

read_gamut_remap(dpp, arr_reg_val, &select);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

253

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

281

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

282

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

283

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

284

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

299

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

308

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

311

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

321

dpp1_cm_program_color_matrix(dpp, regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

325

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

328

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

329

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

330

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

331

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

332

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

333

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

334

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

335

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

337

reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

338

reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

339

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

340

reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

341

reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

342

reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

343

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

344

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

345

reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

346

reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

347

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

348

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

352

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

355

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

356

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

357

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

358

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

359

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

360

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

361

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

362

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

364

reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

365

reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

366

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

367

reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

368

reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

369

reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

370

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

371

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

372

reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

373

reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

374

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

375

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

378

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

381

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

383

dpp1_cm_program_color_matrix(dpp, regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

386

void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

389

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

396

void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

401

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

420

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

423

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

43

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

434

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

437

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

440

dpp1_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

457

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

46

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

463

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

466

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

469

dpp1_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

486

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

490

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

495

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

50

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

538

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

539

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

540

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

541

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

556

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

566

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

569

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

587

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

590

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

593

dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

611

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

616

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

619

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

622

dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

639

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

643

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

646

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

654

struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

656

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

663

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

666

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

690

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

693

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

703

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

708

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

724

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

731

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

753

void dpp1_set_degamma_pwl(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

771

void dpp1_full_bypass(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

773

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

786

if (dpp->tf_mask->CM_BYPASS_EN)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

795

static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

800

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

827

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

831

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

876

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

879

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

92

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

124

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

158

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

161

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

163

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

168

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

169

dpp->base.ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

170

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

180

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

187

if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

207

if (dpp->base.caps->max_lb_partitions == 31)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

241

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

279

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

321

filter_updated = (filter_h && (filter_h != dpp->filter_h))

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

322

|| (filter_v && (filter_v != dpp->filter_v));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

329

filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

330

|| (filter_v_c && (filter_v_c != dpp->filter_v_c));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

338

dpp, scl_data->taps.h_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

341

dpp->filter_h = filter_h;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

344

dpp, scl_data->taps.v_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

347

dpp->filter_v = filter_v;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

351

dpp, scl_data->taps.h_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

356

dpp, scl_data->taps.v_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

360

dpp->filter_h_c = filter_h_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

361

dpp->filter_v_c = filter_v_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

364

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

365

dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

44

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

459

static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

468

if (dpp->base.ctx->dc->debug.use_max_lb) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

47

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

475

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

482

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

491

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

499

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

51

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

511

struct dcn10_dpp *dpp, const struct scaler_data *data)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

587

static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

613

void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

617

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

623

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

628

dpp->scl_data = *scl_data;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

646

dpp1_dscl_set_recout(dpp, &scl_data->recout);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

665

lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

666

dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

685

dpp1_dscl_set_manual_ratio_init(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

694

dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

105

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

317

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

320

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

340

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

344

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

369

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

407

struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

414

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

416

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

417

dpp->base.funcs = &dcn20_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

418

dpp->base.caps = &dcn20_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

42

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

420

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

421

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

422

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

424

dpp->lb_pixel_depth_supported =

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

430

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

431

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

45

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

49

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

51

void dpp20_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

54

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

78

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

81

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

93

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

98

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

29

#define TO_DCN20_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

30

container_of(dpp, struct dcn20_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

678

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

709

void dpp20_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

713

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

717

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

721

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

725

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

731

struct dpp *dpp_base, const struct pwl_params *params);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

734

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

738

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

742

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

759

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

763

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

767

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

772

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

783

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

786

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1014

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1020

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1035

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1039

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1050

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1055

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1084

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1089

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1105

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1108

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1116

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

117

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1196

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1199

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

135

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

138

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

162

struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

189

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

190

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

191

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

192

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

203

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

214

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

217

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

222

program_gamut_remap(dpp, NULL, DCN2_GAMUT_REMAP_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

233

program_gamut_remap(dpp, arr_reg_val, DCN2_GAMUT_REMAP_COEF_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

237

static void read_gamut_remap(struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

250

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

251

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

252

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

253

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

259

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

267

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

273

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

276

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

280

read_gamut_remap(dpp, arr_reg_val, &select);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

293

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

298

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

339

icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

340

icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

341

icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

342

icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

357

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

366

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

369

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

37

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

377

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

380

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

390

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

395

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

414

struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

417

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

418

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

419

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

420

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

421

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

422

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

423

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

424

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

426

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

427

reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

428

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

429

reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

43

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

430

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

431

reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

432

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

433

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

434

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

435

reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

436

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

437

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

442

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

445

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

448

dcn20_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

465

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

47

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

470

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

473

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

476

dcn20_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

493

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

496

static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

500

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

51

struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

523

struct dpp *dpp_base, const struct pwl_params *params)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

527

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

53

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

558

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

566

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

589

static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

593

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

616

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

619

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

631

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

635

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

65

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

70

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

781

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

785

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

86

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

93

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

932

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

938

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

968

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

974

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

191

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

198

dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

203

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

204

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

251

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

298

struct dcn201_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

305

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

307

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

308

dpp->base.funcs = &dcn201_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

309

dpp->base.caps = &dcn201_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

311

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

312

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

313

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

315

dpp->lb_pixel_depth_supported =

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

320

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

321

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

35

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

38

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

42

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

45

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

52

struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

30

#define TO_DCN201_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

31

container_of(dpp, struct dcn201_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

58

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

105

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1063

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1067

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

110

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1213

static bool dpp3_program_shaper(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1219

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1254

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1260

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1301

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1307

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1322

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1326

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1337

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1342

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1371

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1376

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1392

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1395

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1402

static bool dpp3_program_3dlut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

150

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

151

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

152

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1524

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

153

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1531

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1533

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1534

dpp->base.funcs = &dcn30_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1535

dpp->base.caps = &dcn30_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1537

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1538

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1539

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

168

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

178

void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

180

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

221

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

228

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

34

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

37

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

401

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

405

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

41

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

439

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

44

void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

46

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

487

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

488

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

501

dpp->caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

526

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

540

static void dpp3_deferred_update(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

543

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

588

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

591

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

605

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

608

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

622

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

625

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

639

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

642

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

652

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

657

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

688

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

691

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

692

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

693

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

694

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

695

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

696

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

697

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

698

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

700

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

701

reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

702

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

703

reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

704

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

705

reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

706

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

707

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

708

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

709

reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

710

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

711

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

716

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

719

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

722

dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

739

cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

744

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

747

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

750

dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

767

cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

770

static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

776

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

801

static bool dpp3_program_blnd_lut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

806

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

840

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

848

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

87

void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

871

static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

875

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

89

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

898

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

901

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

913

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

917

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

30

#define TO_DCN30_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

31

container_of(dpp, struct dcn3_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

561

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

588

struct dpp *dpp_base, const struct pwl_params *params);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

591

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

594

void dpp30_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

597

void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

600

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

605

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

613

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

617

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

621

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

624

void dpp3_set_pre_degam(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

628

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

632

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

638

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

642

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

645

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

127

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

130

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

146

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

149

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

157

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

160

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

169

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

173

reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

174

reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

175

reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

176

reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

178

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

179

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

180

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

181

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

182

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

183

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

184

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

185

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

187

reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

188

reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

189

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

190

reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

191

reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

192

reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

193

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

194

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

195

reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

196

reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

197

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

198

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

202

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

205

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

216

struct dpp *dpp_base, const struct pwl_params *params)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

220

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

290

dpp3_gamcor_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

305

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

308

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

315

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

34

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

341

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

342

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

343

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

344

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

352

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

362

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

37

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

374

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

377

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

383

program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

405

program_gamut_remap(dpp, arr_reg_val, gamut_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

409

static void read_gamut_remap(struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

41

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

421

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

422

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

423

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

424

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

430

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

438

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

44

struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

444

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

447

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

451

read_gamut_remap(dpp, arr_reg_val, &select);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

46

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

57

static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

62

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

78

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

84

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

148

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

155

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

157

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

158

dpp->base.funcs = &dcn32_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

159

dpp->base.caps = &dcn32_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

161

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

162

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

163

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

130

struct dcn3_dpp *dpp, struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

135

bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

139

dpp->base.funcs = &dcn35_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

142

if (dpp->base.ctx->asic_id.hw_internal_rev < 0x40)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

143

dpp->dispclk_r_gate_disable = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

147

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

31

#define REG(reg) dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

33

#define CTX dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

37

((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

38

((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

41

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

45

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

48

if (dpp->tf_mask->DPPCLK_RATE_CONTROL)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

53

if (dpp->dispclk_r_gate_disable)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

61

if (dpp->dispclk_r_gate_disable)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

71

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

74

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

53

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

62

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

64

void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

263

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

270

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

272

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

273

dpp->base.funcs = &dcn401_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

274

dpp->base.caps = &dcn401_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

276

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

277

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

278

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

36

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

39

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

43

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

45

void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

47

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

56

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

63

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

32

#define TO_DCN401_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

33

container_of(dpp, struct dcn401_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

667

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

703

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

707

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

715

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

719

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

726

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

742

void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

745

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

129

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

135

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

148

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

151

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

170

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

174

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

212

cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

213

cur_matrix_regs.masks.csc_c11 = dpp->tf_mask->CUR0_MATRIX_C11_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

214

cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

215

cur_matrix_regs.masks.csc_c12 = dpp->tf_mask->CUR0_MATRIX_C12_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

226

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

236

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

43

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

46

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

50

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

92

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

95

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1008

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1022

dpp, scl_data->taps.v_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1029

dpp, scl_data->taps.h_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1048

void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1052

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1068

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1075

(dpp->scl_data.dscl_prog_data.sharpness_level

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1078

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1079

dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1080

memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1083

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1088

dpp->scl_data = *scl_data;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1090

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1116

dpp401_dscl_set_recout(dpp, rect);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1135

lb_config = dpp401_dscl_find_lb_memory_config(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1136

dpp401_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1139

if (dpp->base.ctx->dc->config.prefer_easf)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1159

dpp401_dscl_set_manual_ratio_init(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

116

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1177

dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1179

if (dpp->base.ctx->dc->config.prefer_easf)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

150

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

153

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

155

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

160

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

161

dpp->base.ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

162

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

172

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

179

if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

199

if (dpp->base.caps->max_lb_partitions == 31)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

233

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

271

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

288

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

329

filter_updated = (filter_h && (filter_h != dpp->filter_h))

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

330

|| (filter_v && (filter_v != dpp->filter_v));

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

333

filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

334

|| (filter_v_c && (filter_v_c != dpp->filter_v_c));

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

342

dpp, scl_data->taps.h_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

345

dpp->filter_h = filter_h;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

348

dpp, scl_data->taps.v_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

351

dpp->filter_v = filter_v;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

355

dpp, scl_data->taps.h_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

360

dpp, scl_data->taps.v_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

364

dpp->filter_h_c = filter_h_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

365

dpp->filter_v_c = filter_v_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

368

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

369

dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

44

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

465

static enum lb_memory_config dpp401_dscl_find_lb_memory_config(struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

47

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

474

if (dpp->base.ctx->dc->debug.use_max_lb) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

481

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

488

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

497

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

505

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

51

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

517

struct dcn401_dpp *dpp, const struct scaler_data *data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

521

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

634

static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

658

static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

660

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

773

static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

775

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

878

static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

880

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

907

static void dpp401_dscl_disable_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

909

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

921

struct dcn401_dpp *dpp, const uint32_t *filter)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

950

static void dpp401_dscl_program_isharp(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

955

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1447

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1489

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1500

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1506

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1515

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1525

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1532

dpp->funcs->dpp_dppclk_control(dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1543

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1643

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1668

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1674

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1675

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1676

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2035

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2113

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2118

if (dpp == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2121

dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2125

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2132

&dpp->regamma_params, false)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2133

dpp->funcs->dpp_program_regamma_pwl(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2134

dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2135

&dpp->regamma_params, OPP_REGAMMA_USER);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2137

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2142

dpp->regamma_params.hw_points_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2790

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2820

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2833

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2849

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2853

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2854

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2858

static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2863

dpp->funcs->dpp_setup(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2872

if (dpp->funcs->dpp_program_bias_and_scale)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2873

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2973

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2974

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2984

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3029

dpp->funcs->dpp_dppclk_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3030

dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3037

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3068

dcn10_update_dpp(dpp, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3200

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3201

pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3650

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3867

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3876

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3877

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3888

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3903

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3904

pipe_ctx->plane_res.dpp, &opt_attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

464

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

467

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

468

if (dpp->funcs->dpp_get_gamut_remap) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

469

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

477

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

523

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

524

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

525

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

526

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

527

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

528

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

529

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

530

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

531

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

532

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

533

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

534

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

535

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

536

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

199

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

103

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1057

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1077

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1105

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1274

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1283

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

151

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

152

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

153

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

154

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

155

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

156

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

157

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

158

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1585

if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

159

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

160

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

161

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

162

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

163

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

164

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1671

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1678

dpp->funcs->dpp_dppclk_control(dpp, false, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1681

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1732

dpp->funcs->dpp_setup(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1739

if (dpp->funcs->set_cursor_matrix) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1740

dpp->funcs->set_cursor_matrix(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1744

if (dpp->funcs->dpp_program_bias_and_scale) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1746

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1766

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1767

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3167

struct dpp *dpp = res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3169

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3187

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3193

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3194

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3195

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

605

struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

699

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

716

dpp->funcs->dpp_dppclk_control(dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

721

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

90

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

93

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

94

if (dpp->funcs->dpp_get_gamut_remap) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

95

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

291

struct dpp *dpp = res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

293

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

311

struct dpp *dpp = res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

317

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

318

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

319

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

384

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

567

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

568

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

105

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1250

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1261

if (dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1262

if (dpp->funcs->dpp_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1263

dpp->funcs->dpp_read_reg_state(dpp, out_data->dpp_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

160

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

161

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

162

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

163

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

164

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

165

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

166

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

167

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

168

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

169

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

170

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

171

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

172

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

173

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

237

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

259

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

321

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

376

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

91

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

94

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

96

if (dpp->funcs->dpp_get_gamut_remap) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

97

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

458

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

557

struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

558

if (dpp && dpp->funcs->dpp_force_disable_cursor)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

559

dpp->funcs->dpp_force_disable_cursor(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

449

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

486

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

535

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1046

if (j == PG_DPP && new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1047

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1049

if (j == PG_MPCC && new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1074

cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1075

new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1076

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1639

if (pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1640

pipe->plane_res.dpp->cursor_offload = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1653

if (pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1654

pipe->plane_res.dpp->cursor_offload = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1677

const struct dpp *dpp = pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1681

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1705

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1706

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1707

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1708

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1711

p->CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS = dpp->att.fp_scale_bias.bits.fp_bias;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1712

p->CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE = dpp->att.fp_scale_bias.bits.fp_scale;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

483

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

695

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

720

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

726

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

727

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

728

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

819

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

827

dpp->funcs->dpp_dppclk_control(dpp, false, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

859

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

877

dpp->funcs->dpp_dppclk_control(dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

882

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

954

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

957

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1085

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1233

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2870

if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2951

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2967

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2973

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2983

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2991

const struct dpp *dpp = pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2995

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3019

p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3020

p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3021

p->CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3022

p->CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3027

dpp->att.fp_scale_bias_g_y.bits.fp_bias_g_y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3029

dpp->att.fp_scale_bias_g_y.bits.fp_scale_g_y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3031

dpp->att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3033

dpp->att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3043

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3060

hwss_add_dpp_pg_control(seq_state, hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3069

hwss_add_dpp_reset(seq_state, dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3078

hwss_add_dpp_root_clock_control(seq_state, hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3088

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3458

hwss_add_dpp_dppclk_control(seq_state, pipe_ctx->plane_res.dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3462

dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3532

if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3540

hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3548

hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3592

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3598

if (!hubp || !dpp || !plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3603

hwss_add_dpp_dppclk_control(seq_state, dpp, false, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3607

hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3645

if (dpp->funcs->set_cursor_matrix) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3646

hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3651

if (dpp->funcs->dpp_program_bias_and_scale)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3674

hwss_add_dpp_set_scaler(seq_state, pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3926

hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

418

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

622

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

118

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

121

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1686

struct dpp *dpp, uint32_t hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1841

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1892

struct dpp *dpp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1955

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1978

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

311

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

46

struct dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

568

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

594

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

673

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

684

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

126

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

129

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

68

struct dpp;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

249

struct dpp *dpps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

383

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

227

struct dpp *dpp_base, const struct pwl_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

229

void (*dpp_set_pre_degam)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

232

void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

236

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

239

void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

241

void (*dpp_read_reg_state)(struct dpp *dpp, struct dcn_dpp_reg_state *dpp_reg_state);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

243

void (*dpp_reset)(struct dpp *dpp);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

245

void (*dpp_set_scaler)(struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

249

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

254

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

259

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

263

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

267

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

271

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

275

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

280

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

284

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

288

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

292

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

297

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

301

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

305

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

308

void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

312

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

319

void (*dpp_full_bypass)(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

322

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

326

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

334

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

338

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

342

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

347

struct dpp *dpp);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

349

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

352

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

355

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

358

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

361

void (*dpp_get_gamut_remap)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

364

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

368

void (*dpp_force_disable_cursor)(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

231

int dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

308

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

309

cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1138

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1399

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1400

dc->caps.color.dpp.input_lut_shared = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1401

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1402

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1403

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1404

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1405

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1406

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1407

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1408

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1409

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1410

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1412

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1413

dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1414

dc->caps.color.dpp.ogam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1415

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1416

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1417

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1418

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1419

dc->caps.color.dpp.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

594

static void dcn10_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

596

kfree(TO_DCN10_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

597

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

600

static struct dpp *dcn10_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

604

struct dcn10_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

607

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

610

dpp1_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

612

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1529

next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1585

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2201

sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2473

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2474

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2475

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2476

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2477

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2478

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2479

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2480

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2481

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2482

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2483

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2484

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2486

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2487

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2489

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2490

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2491

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2492

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2493

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2494

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

756

void dcn20_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

758

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

759

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

762

struct dpp *dcn20_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

766

struct dcn20_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

769

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

772

if (dpp2_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

774

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

777

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

80

void dcn20_dpp_destroy(struct dpp **dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

82

struct dpp *dcn20_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1057

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1155

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1156

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1157

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1158

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1159

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1160

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1161

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1162

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1163

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1164

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1165

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1166

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1168

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1169

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1171

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1172

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1173

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1174

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1175

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1176

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

625

static void dcn201_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

627

kfree(TO_DCN201_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

628

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

631

static struct dpp *dcn201_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

635

struct dcn201_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

638

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

641

if (dpp201_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

643

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

645

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1452

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1453

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1454

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1455

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1456

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1457

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1458

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1459

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1460

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1461

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1462

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1463

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1465

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1466

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1468

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1469

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1470

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1471

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1472

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1473

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

519

static struct dpp *dcn21_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

523

struct dcn20_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

526

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

529

if (dpp2_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

531

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

534

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1570

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2354

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2355

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2356

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2357

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2358

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2359

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2360

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2361

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2362

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2363

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2364

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2365

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2367

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2368

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2370

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2371

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2372

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2373

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2374

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2375

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

746

static void dcn30_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

748

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

749

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

752

static struct dpp *dcn30_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

756

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

759

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

762

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

764

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

767

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1483

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1484

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1485

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1486

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1487

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1488

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1489

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1490

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1491

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1492

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1493

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1494

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1496

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1497

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1499

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1500

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1501

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1502

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1503

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1504

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

712

static void dcn301_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

714

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

715

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

718

static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

720

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

723

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

726

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

728

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

731

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1277

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1278

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1279

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1280

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1281

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1282

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1283

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1284

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1285

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1286

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1287

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1288

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1290

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1291

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1293

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1294

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1295

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1296

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1297

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1298

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

569

static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

571

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

573

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

576

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

577

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

580

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1221

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1222

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1223

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1224

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1225

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1226

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1227

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1228

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1229

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1230

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1231

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1232

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1234

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1235

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1237

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1238

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1239

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1240

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1241

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1242

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

547

static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

549

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

551

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

554

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

555

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

558

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1957

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1958

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1959

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1960

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1961

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1962

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1963

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1964

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1965

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1966

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1967

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1968

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1970

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1971

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1973

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1974

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1975

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1976

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1977

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1978

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

927

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

929

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

930

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

933

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

937

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

940

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

943

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

945

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

948

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1888

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1889

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1890

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1891

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1892

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1893

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1894

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1895

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1896

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1897

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1898

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1899

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1901

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1902

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1904

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1905

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1906

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1907

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1908

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1909

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

929

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

963

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

965

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

966

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

969

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

973

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

976

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

979

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

981

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

984

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1926

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1927

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1928

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1929

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1930

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1931

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1932

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1933

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1934

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1935

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1936

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1937

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1939

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1940

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1942

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1943

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1944

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1945

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1946

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1947

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

926

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

928

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

929

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

932

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

936

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

939

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

942

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

944

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

947

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1801

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1802

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1803

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1804

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1805

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1806

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1807

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1808

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1809

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1810

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1811

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1812

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1814

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1815

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1817

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1818

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1819

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1820

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1821

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1822

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

919

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

921

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

922

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

925

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

929

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

932

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

935

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

937

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

940

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2280

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2281

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2282

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2283

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2284

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2285

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2286

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2287

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2288

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2289

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2290

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2291

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2293

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2294

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2296

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2297

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2298

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2299

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2300

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2301

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2809

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2868

free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2901

free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

946

static void dcn32_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

948

kfree(TO_DCN30_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

949

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

952

static struct dpp *dcn32_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1779

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1780

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1781

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1782

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1783

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1784

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1785

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1786

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1787

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1788

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1789

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1790

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1792

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1793

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1795

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1796

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1797

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1798

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1799

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1800

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

940

static void dcn321_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

942

kfree(TO_DCN30_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

943

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

946

static struct dpp *dcn321_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1915

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1916

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1917

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1918

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1919

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1920

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1921

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1922

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1923

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1924

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1925

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1926

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1928

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1929

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1931

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1932

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1933

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1934

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1935

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1936

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

766

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

819

static void dcn35_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

821

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

822

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

825

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

827

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

828

bool success = (dpp != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

840

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

844

dpp,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

845

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

846

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

850

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1888

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1889

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1890

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1891

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1892

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1893

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1894

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1895

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1896

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1897

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1898

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1899

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1901

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1902

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1904

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1905

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1906

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1907

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1908

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1909

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

746

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

799

static void dcn35_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

801

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

802

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

805

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

807

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

808

bool success = (dpp != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

820

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

824

dpp,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

825

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

826

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

830

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1894

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1895

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1896

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1897

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1898

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1899

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1900

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1901

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1902

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1903

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1904

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1905

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1907

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1908

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1910

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1911

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1912

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1913

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1914

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1915

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

753

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

806

static void dcn35_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

808

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

809

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

812

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

814

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

815

bool success = (dpp != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

827

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

831

dpp,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

832

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

833

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

837

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1960

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1961

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1962

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1963

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1964

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1965

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1966

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1967

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1968

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1969

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1970

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1971

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1973

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1974

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1976

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1977

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1978

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1979

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1980

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1981

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

942

static void dcn401_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

944

kfree(TO_DCN401_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

945

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

948

static struct dpp *dcn401_dpp_create(

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1697

dc_caps->dpp.dcn_arch == 1) {

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1700

dc_caps->dpp.dgam_rom_caps.pq == 1)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1704

dc_caps->dpp.dgam_rom_caps.gamma2_2 == 1)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1709

dc_caps->dpp.dgam_rom_caps.hlg == 1)

fs/nfsd/vfs.c

125

nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp,

fs/nfsd/vfs.c

129

struct dentry *dentry = *dpp;

fs/nfsd/vfs.c

172

*dpp = path.dentry;

fs/nfsd/vfs.h

76

int nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp,

fs/xfs/libxfs/xfs_dquot_buf.c

486

struct xfs_inode **dpp)

fs/xfs/libxfs/xfs_dquot_buf.c

493

return xfs_metadir_mkdir(mp->m_metadirip, "quota", dpp);

fs/xfs/libxfs/xfs_dquot_buf.c

504

struct xfs_inode **dpp)

fs/xfs/libxfs/xfs_dquot_buf.c

514

dpp);

fs/xfs/libxfs/xfs_quota_defs.h

184

int xfs_dqinode_mkdir_parent(struct xfs_mount *mp, struct xfs_inode **dpp);

fs/xfs/libxfs/xfs_quota_defs.h

185

int xfs_dqinode_load_parent(struct xfs_trans *tp, struct xfs_inode **dpp);

fs/xfs/scrub/parent.c

414

struct xfs_inode **dpp)

fs/xfs/scrub/parent.c

448

*dpp = ip;