dpll_state
struct intel_dpll_state dpll_state[I915_NUM_PLLS];
struct intel_dpll_state *dpll_state)
dpll_state[pll->index] = pll->state;
state->dpll_state);
return state->dpll_state;
struct intel_dpll_state *dpll_state;
dpll_state = intel_atomic_get_dpll_state(&state->base);
if (dpll_state[pll->index].pipe_mask == 0) {
&dpll_state[pll->index].hw_state,
dpll_state[pll->index].pipe_mask,
struct intel_dpll_state *dpll_state)
drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
dpll_state->pipe_mask |= BIT(crtc->pipe);
struct intel_dpll_state *dpll_state;
dpll_state = intel_atomic_get_dpll_state(&state->base);
if (dpll_state[pll->index].pipe_mask == 0)
dpll_state[pll->index].hw_state = *dpll_hw_state;
intel_dpll_crtc_get(crtc, pll, &dpll_state[pll->index]);
struct intel_dpll_state *dpll_state)
drm_WARN_ON(display->drm, (dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
dpll_state->pipe_mask &= ~BIT(crtc->pipe);
struct intel_dpll_state *dpll_state;
dpll_state = intel_atomic_get_dpll_state(&state->base);
intel_dpll_crtc_put(crtc, pll, &dpll_state[pll->index]);
struct intel_dpll_state *dpll_state = state->dpll_state;
swap(pll->state, dpll_state[pll->index]);
u8 dpll_state;
u8 *dpll_state, u8 *config, s64 *phase_offset,
*dpll_state = cmd->dpll_state;
u8 *dpll_state, u8 *config, s64 *phase_offset,
if (d->prev_dpll_state != d->dpll_state) {
d->prev_dpll_state = d->dpll_state;
&d->phase_offset, &d->dpll_state);
d->dpll_state, d->prev_dpll_state, d->mode);
if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED ||
d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ)
if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER ||
d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) {
*status = d->dpll_state;
enum dpll_lock_status dpll_state;
enum dpll_lock_status *dpll_state)
if (!dpll_state)
*dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ;
*dpll_state = DPLL_LOCK_STATUS_LOCKED;
*dpll_state = DPLL_LOCK_STATUS_HOLDOVER;
*dpll_state = DPLL_LOCK_STATUS_UNLOCKED;
enum dpll_lock_status *dpll_state);