dpi_reg_write
dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
dpi_reg_write(dpi, DPI_DMAX_IBUFF_CSIZE(vf), reg);
dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), reg);
dpi_reg_write(dpi, DPI_DMAX_IDS(vf), reg);
dpi_reg_write(dpi, DPI_DMAX_QRST(vf), DPI_DMA_QRST);
dpi_reg_write(dpi, DPI_DMAX_IDS2(vf), 0);
dpi_reg_write(dpi, DPI_DMAX_IDS(vf), 0);
dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT, reg);
dpi_reg_write(dpi, DPI_ENGX_BUF(engine), reg);
dpi_reg_write(dpi, DPI_DMA_CONTROL, reg);
dpi_reg_write(dpi, DPI_CTL, DPI_CTL_EN);
dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(port), reg);
dpi_reg_write(dpi, DPI_WCTL_FIF_THR, DPI_WCTL_FIFO_THRESHOLD);
dpi_reg_write(dpi, DPI_ENGX_BUF(engine), 0);
dpi_reg_write(dpi, DPI_DMA_CONTROL, 0);
dpi_reg_write(dpi, DPI_CTL, 0);
dpi_reg_write(dpi, DPI_PF_RAS, DPI_PF_RAS_INT);
dpi_reg_write(dpi, DPI_PF_RAS_ENA_W1C, DPI_PF_RAS_INT);
dpi_reg_write(dpi, DPI_REQQX_INT(i), DPI_REQQ_INT);
dpi_reg_write(dpi, DPI_REQQX_INT_ENA_W1C(i), DPI_REQQ_INT);
dpi_reg_write(dpi, DPI_DMA_CCX_INT(i), DPI_DMA_CC_INT);
dpi_reg_write(dpi, DPI_DMA_CCX_INT_ENA_W1C(i), DPI_DMA_CC_INT);
dpi_reg_write(dpi, DPI_MBOX_VF_PF_INT_ENA_W1S, GENMASK_ULL(31, 0));
dpi_reg_write(dpi, DPI_EBUS_PORTX_CFG(cfg.port), reg);
dpi_reg_write(dpi, DPI_ENGX_BUF(engine), eng_buf[engine]);
dpi_reg_write(dpi, DPI_DMA_ENGX_EN(engine), reg);