dispc_vp_write
dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
dispc_vp_write(tidss->dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
dispc_vp_write(_dispc, _vp, _idx, _reg); \
dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);