drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1247

struct dmub_srv *dmub_srv = adev->dm.dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1260

if (!dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1276

if (dmub_srv->hw_funcs.init_reg_offsets)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1277

dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1279

status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1291

status = dmub_srv_hw_reset(dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13111

if (adev->dm.dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13392

if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13424

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13425

ctx->dmub_srv->reg_helper_offload.gather_in_progress &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13426

!ctx->dmub_srv->reg_helper_offload.should_burst_write) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13599

return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13604

return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1378

status = dmub_srv_hw_init(dmub_srv, &hw_params);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1385

status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1395

if (!adev->dm.dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1396

adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1397

if (!adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1433

struct dmub_srv *dmub_srv = adev->dm.dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1438

if (!dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1443

status = dmub_srv_is_hw_init(dmub_srv, &init);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1449

status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2261

dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2442

struct dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2527

adev->dm.dmub_srv = kzalloc_obj(*adev->dm.dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2528

dmub_srv = adev->dm.dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2530

if (!dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2542

status = dmub_srv_create(dmub_srv, &create_params);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2580

status = dmub_srv_calc_region_info(dmub_srv, &region_params,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2617

status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2670

if (adev->dm.dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2671

dmub_srv_destroy(adev->dm.dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2672

kfree(adev->dm.dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2673

adev->dm.dmub_srv = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2750

} else if (adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3245

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3490

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3523

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3582

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4012

if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4815

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5188

if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

362

struct dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

95

struct dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1034

if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1036

(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2692

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3311

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3355

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

924

if (adev->dm.dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

925

fw_meta_info = &adev->dm.dmub_srv->meta_info;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

98

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

99

!dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1059

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1061

enable_lvtma_control_dmcub(bp->base.ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

180

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

182

encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

196

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

296

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

298

transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

378

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

406

transmitter_control_dmcub_v1_7(bp->base.ctx->dmub_srv, &dig_v1_7);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

425

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

553

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

555

set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

569

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

862

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

864

enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

880

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1303

memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1580

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/dc/core/dc.c

2332

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);

drivers/gpu/drm/amd/display/dc/core/dc.c

4271

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

4540

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

4612

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);

drivers/gpu/drm/amd/display/dc/core/dc.c

5562

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

5573

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/dc/core/dc.c

5582

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

559

dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

5757

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

5760

return dc->ctx->dmub_srv->idle_allowed;

drivers/gpu/drm/amd/display/dc/core/dc.c

579

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

597

struct dc_dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

5976

dmub_enable_outbox_notification(dc_ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

617

dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

620

if (dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

621

dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);

drivers/gpu/drm/amd/display/dc/core/dc.c

6307

dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

632

dc_stream_forward_dmub_multiple_crc_window(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

656

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

663

struct dc_dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

682

dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

685

if (dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

686

dc_stream_forward_dmub_multiple_crc_window(dmub_srv, window, &mux_mapping, stop);

drivers/gpu/drm/amd/display/dc/core/dc.c

7156

dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

645

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

718

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

813

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

55

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

85

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

285

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

436

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

109

struct dmub_srv *dmub = dc_dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1155

bool dc_dmub_check_min_version(struct dmub_srv *srv)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1164

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1194

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

122

struct dmub_srv *dmub = dc_dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1339

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1342

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

136

struct dmub_srv *dmub = dc_dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1368

dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1460

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1463

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

152

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1547

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1555

dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1578

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1591

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1662

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1719

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1752

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1779

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1870

struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1880

cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

194

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2076

dmub_flush_buffer_mem(&ctx->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2083

cmd.ips_query_residency_info.info_data.dest.quad_part = ctx->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2093

memcpy(driver_info, ctx->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2115

lsdma_data->u.init_data.gpu_addr_base.quad_part = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2116

lsdma_data->u.init_data.ring_size = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.size;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2349

return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2354

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2372

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

272

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

322

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

354

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

376

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

47

struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

559

memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

60

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

75

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

77

if (*dmub_srv) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

78

kfree(*dmub_srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

79

*dmub_srv = NULL;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

85

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

104

bool dc_dmub_check_min_version(struct dmub_srv *srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

32

struct dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

49

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

94

void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

95

void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

96

void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dc/dc_helper.c

146

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

171

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

210

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

237

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

238

ctx->dmub_srv->reg_helper_offload.gather_in_progress)

drivers/gpu/drm/amd/display/dc/dc_helper.c

267

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

268

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

436

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

437

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

494

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

495

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

633

if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

635

&ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

648

if (!ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_helper.c

651

offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

677

if (!ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_helper.c

680

offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

685

dc_dmub_srv_wait_for_idle(ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

drivers/gpu/drm/amd/display/dc/dc_types.h

825

struct dc_dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

169

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

172

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

178

cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

229

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

232

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)pData, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

238

cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

249

memcpy((void *)pData, dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

102

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

31

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

50

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

53

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

59

dc_dmub_srv_clear_inbox0_ack(dmub_srv);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

60

dc_dmub_srv_send_inbox0_cmd(dmub_srv, data);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

61

dc_dmub_srv_wait_for_inbox0_ack(dmub_srv);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

32

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

37

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c

39

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv)

drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c

51

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h

31

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

199

dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

44

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

71

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

105

struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dm_services.h

127

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dc/dm_services.h

128

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);

drivers/gpu/drm/amd/display/dc/dm_services.h

41

struct dmub_srv;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1010

if (ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

855

if (ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1788

if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2256

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1455

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1850

params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

828

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

829

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

830

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

921

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

274

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

275

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

276

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

436

if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1002

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1006

} else if (dc->ctx->dmub_srv->dmub->fw_version <

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

268

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

357

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

424

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

442

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

993

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

994

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

995

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

996

dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

997

dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

999

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1622

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1645

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1663

shared_stream = &dc->ctx->dmub_srv->dmub->shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1]

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1674

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

269

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

313

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

314

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

315

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

316

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

317

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1290

if (!dc->ctx->dmub_srv || !dc->current_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1496

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1506

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1521

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1529

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1789

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1811

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2988

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

359

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

360

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

361

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

363

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3752

hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

888

dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

936

dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1507

if (!link->ctx->dmub_srv ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

117

struct dc_dmub_srv *dmub_srv = link->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

126

if (dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1012

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1024

enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1039

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1051

void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1064

enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1074

void dmub_srv_cmd_get_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1087

enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1104

enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1118

enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1128

bool dmub_srv_get_preos_info(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

451

void (*init)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

453

void (*reset)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

455

void (*reset_release)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

457

void (*backdoor_load)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

461

void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

464

void (*setup_windows)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

472

void (*setup_mailbox)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

475

uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

477

uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

479

void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

481

void (*setup_out_mailbox)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

484

uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

486

void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

488

void (*setup_outbox0)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

491

uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

493

void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

495

uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

497

uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

499

void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

501

bool (*is_supported)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

503

bool (*is_psrsu_supported)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

505

bool (*is_hw_init)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

506

bool (*is_hw_powered_up)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

508

void (*enable_dmub_boot_options)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

511

void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

513

union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

515

union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

517

void (*set_gpint)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

520

bool (*is_gpint_acked)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

523

uint32_t (*get_gpint_response)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

525

uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

527

void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

528

void (*clear_inbox0_ack_register)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

529

uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

530

void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

531

uint32_t (*get_current_time)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

533

void (*get_diagnostic_data)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

534

bool (*get_preos_fw_info)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

536

bool (*should_detect)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

537

void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

539

void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

541

void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

543

uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

544

void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

546

void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

547

void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

548

void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

550

uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

551

void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

552

void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

553

void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

554

uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

555

void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

679

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

686

void dmub_srv_destroy(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

702

dmub_srv_calc_region_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

719

enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

736

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

746

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

761

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

777

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

79

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

792

enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

805

enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

820

enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

823

bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

841

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

860

enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

877

enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

894

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

916

dmub_srv_send_gpint_command(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

933

enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

949

enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

972

enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

975

enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

978

enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

981

bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

983

bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

985

bool dmub_srv_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

998

enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/dmub_srv_stat.h

38

enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

146

void dmub_dcn20_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

154

void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

189

void dmub_dcn20_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

274

void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

286

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

291

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

296

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

301

void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

313

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

322

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

331

void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

339

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

344

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

349

bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

358

bool dmub_dcn20_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

367

void dmub_dcn20_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

373

bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

384

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

389

union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

397

void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

404

void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

412

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

417

void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

60

static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

87

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

94

void dmub_dcn20_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

185

void dmub_dcn20_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

187

void dmub_dcn20_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

189

void dmub_dcn20_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

191

void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

195

void dmub_dcn20_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

203

void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

206

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

208

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

210

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

212

void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

215

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

217

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

219

void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

222

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

224

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

226

bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

228

bool dmub_dcn20_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

230

void dmub_dcn20_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

233

bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

236

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

238

void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

240

void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

242

union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

244

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

246

bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

248

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

250

void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

122

void dmub_dcn30_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

60

static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

87

void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h

37

void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h

41

void dmub_dcn30_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

149

void dmub_dcn31_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

157

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

190

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

244

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

251

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

256

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

261

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

266

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

273

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

282

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

291

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

302

bool dmub_dcn31_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

311

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

316

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

322

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

333

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

338

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

353

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

361

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

369

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

388

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

396

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

404

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

409

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

414

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

419

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

490

bool dmub_dcn31_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

56

static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

83

void dmub_dcn31_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

187

void dmub_dcn31_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

189

void dmub_dcn31_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

191

void dmub_dcn31_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

193

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

197

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

205

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

208

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

210

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

212

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

214

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

217

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

219

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

221

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

223

bool dmub_dcn31_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

225

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

227

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

230

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

233

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

235

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

237

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

239

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

241

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

243

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

245

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

248

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

250

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

252

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

254

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

256

bool dmub_dcn31_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c

64

bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h

33

bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

157

void dmub_dcn32_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

165

void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

200

void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

232

void dmub_dcn32_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

286

void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

293

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

298

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

303

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

308

void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

315

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

324

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

333

bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

344

bool dmub_dcn32_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

353

void dmub_dcn32_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

359

bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

370

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

375

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

390

union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

398

void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

40

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

407

void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

415

void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

423

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

428

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

433

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

438

void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

505

void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

518

void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

523

void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

528

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

533

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

62

static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

89

void dmub_dcn32_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

198

void dmub_dcn32_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

200

void dmub_dcn32_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

202

void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

206

void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

210

void dmub_dcn32_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

218

void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

221

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

223

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

225

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

227

void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

230

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

232

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

234

bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

236

bool dmub_dcn32_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

238

void dmub_dcn32_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

241

bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

244

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

246

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

248

void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

250

void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

252

union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

254

void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

257

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

259

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

261

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

263

void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

265

void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

266

void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

267

void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

268

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

269

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

271

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

148

void dmub_dcn35_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

162

void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

193

void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

217

void dmub_dcn35_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

280

void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

287

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

292

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

297

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

302

void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

309

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

318

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

327

bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

338

bool dmub_dcn35_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

347

void dmub_dcn35_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

353

bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

364

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

369

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

384

union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

392

union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

40

void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) {

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

400

void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

429

void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

437

void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

445

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

450

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

455

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

460

void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

528

bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

566

void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

579

bool dmub_dcn35_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

586

void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

59

static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

591

void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

596

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

601

bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

88

void dmub_dcn35_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

203

void dmub_dcn35_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

205

void dmub_dcn35_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

207

void dmub_dcn35_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

209

void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

213

void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

217

void dmub_dcn35_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

225

void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

228

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

230

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

232

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

234

void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

237

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

239

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

241

bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

243

bool dmub_dcn35_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

245

void dmub_dcn35_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

248

bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

251

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

253

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

255

void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

257

void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

259

union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

261

union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

263

void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

266

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

268

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

270

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

272

void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

274

void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

276

void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

278

void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

280

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

282

bool dmub_dcn35_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

284

bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

286

void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

288

bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

16

void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h

11

void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h

9

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

16

void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h

11

void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h

9

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

131

void dmub_dcn401_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

139

void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

175

void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

208

void dmub_dcn401_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

271

void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

278

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

283

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

288

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

293

void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

300

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

309

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

318

bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

329

bool dmub_dcn401_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

338

void dmub_dcn401_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

344

bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

355

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

36

static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

360

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

375

union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

383

void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

394

void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

402

void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

410

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

415

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

420

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

425

void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

498

void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

511

void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

516

void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

521

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

526

void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

595

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

603

void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

628

void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

63

void dmub_dcn401_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

633

void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

638

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

643

void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

649

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

654

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

659

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

667

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

672

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

10

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

202

void dmub_dcn401_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

204

void dmub_dcn401_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

206

void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

210

void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

214

void dmub_dcn401_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

222

void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

225

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

227

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

229

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

231

void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

234

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

236

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

238

bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

240

bool dmub_dcn401_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

242

void dmub_dcn401_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

245

bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

248

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

250

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

252

void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

254

void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

256

union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

258

void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

261

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

263

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

265

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

267

void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

269

void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

270

void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

271

void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

272

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

274

void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

276

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

277

void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

279

void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

280

void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

281

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

283

void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

284

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

285

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

286

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

287

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

288

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

104

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

72

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

89

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

114

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

117

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

120

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1031

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1058

dmub_srv_send_gpint_command(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1090

enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1106

enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1122

enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1136

enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1150

enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1185

bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1192

bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1200

bool dmub_srv_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1208

enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1217

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1234

enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1244

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1253

void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1261

enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1296

void dmub_srv_cmd_get_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1309

static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1320

static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1341

enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1356

enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1383

enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1413

bool dmub_srv_get_preos_info(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

202

static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

486

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

537

void dmub_srv_destroy(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

563

dmub_srv_calc_region_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

620

enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

654

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

668

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

684

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

846

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

873

enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

895

enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

921

bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

932

enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

950

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

974

static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

993

enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c

46

enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,