devm_clk_hw_register_fixed_factor
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
hw = devm_clk_hw_register_fixed_factor(dev, "pll1_div2", "pll1", 0, 1, 2);
hw = devm_clk_hw_register_fixed_factor(dev, "pll2_div2", "pll2", 0, 1, 2);
hw = devm_clk_hw_register_fixed_factor(dev, "pll_gfx_div2", "pll_gfx", 0, 1, 2);
hw = devm_clk_hw_register_fixed_factor(dev, "pre_clk", "cpu_mux", 0, 1, 2);
hw = devm_clk_hw_register_fixed_factor(dev, "axi", "th", 0, 1, 2);
hw = devm_clk_hw_register_fixed_factor(dev, "atb", "axi", 0, 1, 2);
hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
divhw = devm_clk_hw_register_fixed_factor(dev, outputname,
return devm_clk_hw_register_fixed_factor(dev, name, parent,
clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name, parent_name,
clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name,
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
div_clk = devm_clk_hw_register_fixed_factor(dev,
clk_wzrd->clks_internal[wzrd_clk_mul] = devm_clk_hw_register_fixed_factor
devm_clk_hw_register_fixed_factor(dev, clk_name, clk_mul_name, 0, 1, div);
priv->clkout_clk_hw = devm_clk_hw_register_fixed_factor(dev, name,
struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,