dmt
_ASM_MACRO_1R(dmt, rt, \
dmt();
dmt();
mtflags = dmt();
mtflags = dmt();
mtflags = dmt();
dmt_flag = dmt();
return readl(dmt->regs + DMTPSCNT_REG) / rate;
static inline u32 pic32_dmt_bootstatus(struct pic32_dmt *dmt)
struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
dmt_enable(dmt);
return dmt_keepalive(dmt);
struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
dmt_disable(dmt);
struct pic32_dmt *dmt = watchdog_get_drvdata(wdd);
return dmt_keepalive(dmt);
struct pic32_dmt *dmt;
dmt = devm_kzalloc(dev, sizeof(*dmt), GFP_KERNEL);
if (!dmt)
dmt->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dmt->regs))
return PTR_ERR(dmt->regs);
dmt->clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(dmt->clk)) {
return PTR_ERR(dmt->clk);
wdd->timeout = pic32_dmt_get_timeout_secs(dmt);
wdd->bootstatus = pic32_dmt_bootstatus(dmt) ? WDIOF_CARDRESET : 0;
watchdog_set_drvdata(wdd, dmt);
static inline void dmt_enable(struct pic32_dmt *dmt)
writel(DMT_ON, PIC32_SET(dmt->regs + DMTCON_REG));
static inline void dmt_disable(struct pic32_dmt *dmt)
writel(DMT_ON, PIC32_CLR(dmt->regs + DMTCON_REG));
static inline int dmt_bad_status(struct pic32_dmt *dmt)
val = readl(dmt->regs + DMTSTAT_REG);
static inline int dmt_keepalive(struct pic32_dmt *dmt)
writel(DMT_STEP1_KEY << 8, dmt->regs + DMTPRECLR_REG);
v = readl(dmt->regs + DMTSTAT_REG) & DMTSTAT_WINOPN;
writel(DMT_STEP2_KEY, dmt->regs + DMTCLR_REG);
return dmt_bad_status(dmt);
static inline u32 pic32_dmt_get_timeout_secs(struct pic32_dmt *dmt)
rate = clk_get_rate(dmt->clk);