drivers/gpu/drm/omapdrm/omap_dmm_priv.h

118

struct dmm;

drivers/gpu/drm/omapdrm/omap_dmm_priv.h

132

struct dmm *dmm;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

100

dmaengine_terminate_all(dmm->wa_dma_chan);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

104

static u32 dmm_read_wa(struct dmm *dmm, u32 reg)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

109

src = dmm->phys_base + reg;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

110

dst = dmm->wa_dma_handle;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

112

r = dmm_dma_copy(dmm, src, dst);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

114

dev_err(dmm->dev, "sDMA read transfer timeout\n");

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

115

return readl(dmm->base + reg);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

124

return readl((__iomem void *)dmm->wa_dma_data);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

127

static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

132

writel(val, (__iomem void *)dmm->wa_dma_data);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

141

src = dmm->wa_dma_handle;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

142

dst = dmm->phys_base + reg;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

144

r = dmm_dma_copy(dmm, src, dst);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

146

dev_err(dmm->dev, "sDMA write transfer timeout\n");

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

147

writel(val, dmm->base + reg);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

151

static u32 dmm_read(struct dmm *dmm, u32 reg)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

153

if (dmm->dmm_workaround) {

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

157

spin_lock_irqsave(&dmm->wa_lock, flags);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

158

v = dmm_read_wa(dmm, reg);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

159

spin_unlock_irqrestore(&dmm->wa_lock, flags);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

163

return readl(dmm->base + reg);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

167

static void dmm_write(struct dmm *dmm, u32 val, u32 reg)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

169

if (dmm->dmm_workaround) {

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

172

spin_lock_irqsave(&dmm->wa_lock, flags);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

173

dmm_write_wa(dmm, val, reg);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

174

spin_unlock_irqrestore(&dmm->wa_lock, flags);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

176

writel(val, dmm->base + reg);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

180

static int dmm_workaround_init(struct dmm *dmm)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

184

spin_lock_init(&dmm->wa_lock);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

186

dmm->wa_dma_data = dma_alloc_coherent(dmm->dev, sizeof(u32),

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

187

&dmm->wa_dma_handle, GFP_KERNEL);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

188

if (!dmm->wa_dma_data)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

194

dmm->wa_dma_chan = dma_request_channel(mask, NULL, NULL);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

195

if (!dmm->wa_dma_chan) {

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

196

dma_free_coherent(dmm->dev, 4, dmm->wa_dma_data, dmm->wa_dma_handle);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

203

static void dmm_workaround_uninit(struct dmm *dmm)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

205

dma_release_channel(dmm->wa_dma_chan);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

207

dma_free_coherent(dmm->dev, 4, dmm->wa_dma_data, dmm->wa_dma_handle);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

234

struct dmm *dmm = engine->dmm;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

239

r = dmm_read(dmm, reg[PAT_STATUS][engine->id]);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

242

dev_err(dmm->dev,

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

252

dev_err(dmm->dev,

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

278

struct dmm *dmm = arg;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

279

u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

283

dmm_write(dmm, status, DMM_PAT_IRQSTATUS);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

285

for (i = 0; i < dmm->num_engines; i++) {

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

287

dev_err(dmm->dev,

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

292

if (dmm->engines[i].async)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

293

release_engine(&dmm->engines[i]);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

295

complete(&dmm->engines[i].compl);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

307

static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

323

if (!list_empty(&dmm->idle_head)) {

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

324

engine = list_entry(dmm->idle_head.next, struct refill_engine,

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

38

static struct dmm *omap_dmm;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

382

page_to_phys(pages[n]) : engine->dmm->dummy_pa;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

397

struct dmm *dmm = engine->dmm;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

400

dev_err(engine->dmm->dev, "need at least one txn\n");

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

419

dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

435

dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

440

dev_err(dmm->dev, "timed out waiting for done\n");

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

78

static int dmm_dma_copy(struct dmm *dmm, dma_addr_t src, dma_addr_t dst)

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

84

tx = dmaengine_prep_dma_memcpy(dmm->wa_dma_chan, dst, src, 4, 0);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

86

dev_err(dmm->dev, "Failed to prepare DMA memcpy\n");

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

897

omap_dmm->engines[i].dmm = omap_dmm;

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

92

dev_err(dmm->dev, "Failed to do DMA tx_submit\n");

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

96

status = dma_sync_wait(dmm->wa_dma_chan, cookie);

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

98

dev_err(dmm->dev, "i878 wa DMA copy failure\n");