drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

289

/ dml_pow(

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3466

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3489

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

313

/ dml_pow(

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3573

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3596

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1304

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1305

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1336

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1337

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1379

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1380

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1381

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1382

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1383

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1384

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1386

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1387

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1392

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1399

< (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1405

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1423

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1424

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1428

/ (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1429

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1433

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1438

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1439

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1446

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1447

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1451

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1452

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1459

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1460

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1467

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1468

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1475

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1476

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1482

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1483

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1493

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1495

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1497

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1499

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1501

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1503

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1505

(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1507

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1509

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1523

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1633

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1663

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

921

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

923

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

927

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

936

disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

937

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1305

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1306

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1337

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1338

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1380

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1381

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1382

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1383

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1384

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1385

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1387

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1388

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1393

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1400

< (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1406

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1424

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1425

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1429

/ (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1430

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1434

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1439

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1440

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1447

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1448

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1452

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1453

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1460

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1461

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1468

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1469

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1476

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1477

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1483

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1484

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1494

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1496

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1498

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1500

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1502

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1504

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1506

(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1508

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1510

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1524

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1634

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1664

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

921

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

923

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

927

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

937

+ min_dst_y_ttu_vblank) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

938

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1368

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1369

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1404

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1405

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1449

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1450

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1451

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1452

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1453

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1454

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1456

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1457

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1468

disp_dlg_regs->refcyc_per_pte_group_vblank_l >= (unsigned int)dml_pow(2, 13))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1471

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1478

disp_dlg_regs->refcyc_per_pte_group_vblank_c >= (unsigned int)dml_pow(2, 13))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1482

< (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1491

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1510

disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1511

disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1514

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1515

disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1517

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1518

disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1520

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1521

disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1523

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1524

disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1526

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1527

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1531

/ (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1532

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1537

(unsigned int)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1542

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1543

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1554

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1555

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1559

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1560

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1567

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1568

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1575

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1576

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1583

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1584

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1590

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1591

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1601

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1603

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1605

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1607

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1609

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1611

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1613

(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1615

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1617

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1620

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1631

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1747

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1783

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

967

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

969

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

973

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

982

disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

983

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1038

(unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1040

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1051

) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1052

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1216

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1475

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1476

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1507

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1508

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1551

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1552

disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1553

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1554

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1555

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1556

disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1558

disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1559

disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1569

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1576

< (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1582

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1601

disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1602

disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1605

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1606

disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1608

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1609

disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1611

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1612

disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1614

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1615

disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1618

/ (double)vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1619

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1623

/ (double)vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1624

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int)dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1628

(unsigned int)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1633

/ (double)vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1634

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1643

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1644

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1648

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1649

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1656

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1657

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1664

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1665

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1672

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1673

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1679

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1680

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1690

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1692

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1694

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1696

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1698

(unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1700

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1702

(unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1704

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1706

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1709

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1720

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

849

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

879

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1089

} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1318

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1355

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1403

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1404

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1405

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1406

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1407

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1408

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1410

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1411

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1419

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1423

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1427

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1441

disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1442

disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1445

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1446

disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1448

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1449

disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1451

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1452

disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1454

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1455

disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1457

disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1458

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1460

disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1461

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1466

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1470

disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1471

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1473

disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1474

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1478

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1479

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1482

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1483

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1488

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1489

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1494

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1495

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1500

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1504

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1513

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1514

disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1515

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1516

disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1517

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1518

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1519

disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1520

disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1523

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1526

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1537

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

826

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

841

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

975

disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

976

disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

983

disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

985

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1060

disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1061

disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1070

disp_dlg_regs->min_dst_y_next_start = vba__min_dst_y_next_start * dml_pow(2, 2);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1072

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1177

} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1406

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1443

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1491

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1492

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1493

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1494

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1495

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1496

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1498

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1499

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1507

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1511

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1515

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1529

disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1530

disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1533

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1534

disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1536

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1537

disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1539

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1540

disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1542

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1543

disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1545

disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1546

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1548

disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1549

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1554

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1558

disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1559

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1561

disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1562

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1566

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1567

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1570

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1571

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1576

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1577

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1582

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1583

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1588

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1592

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1601

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1602

disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1603

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1604

disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1605

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1606

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1607

disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1608

disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1611

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1614

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1625

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

912

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

926

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

274

dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

275

dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

344

ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

440

dlg_regs->min_dst_y_next_start = min_dst_y_next_start * dml_pow(2, 2);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

441

ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

445

dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

446

dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

447

dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

448

dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

449

dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

451

dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

452

dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

464

pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

466

pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

503

dlg_regs->dst_y_per_pte_row_nom_l = dst_y_per_pte_row_nom_l * dml_pow(2, 2);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

504

dlg_regs->dst_y_per_pte_row_nom_c = dst_y_per_pte_row_nom_c * dml_pow(2, 2);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

505

dlg_regs->dst_y_per_meta_row_nom_l = dst_y_per_meta_row_nom_l * dml_pow(2, 2);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

506

dlg_regs->dst_y_per_meta_row_nom_c = dst_y_per_meta_row_nom_c * dml_pow(2, 2);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

531

ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

532

ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

533

ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

534

ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

536

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

537

ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

554

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

555

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

556

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

557

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

558

if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

559

dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

561

if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

562

dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

564

if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

565

dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

567

if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

568

dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

571

ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

572

ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

574

if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

577

__func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

580

ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

581

ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

583

if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

584

dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

586

if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

587

dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

589

ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

591

ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

594

if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

595

dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

597

if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

598

dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

600

ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

601

ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

602

ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

603

ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

604

ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

605

ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

606

ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

607

ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

608

ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1153

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1155

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1158

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1175

+ min_dst_y_ttu_vblank) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1176

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1440

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1450

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1461

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1465

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1519

disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1521

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1525

disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1527

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1532

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1537

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1542

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1559

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1560

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1563

/ (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1564

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1567

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1568

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1575

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1576

disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1581

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1582

disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1587

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1588

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1689

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1690

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1728

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1729

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1771

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1773

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1775

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1776

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1808

(unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1810

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1812

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1813

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1860

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1861

ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1895

(unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1896

ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1904

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1907

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1918

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h

49

__DML_DLL_EXPORT__ dml_float_t dml_pow(dml_float_t base, int exp);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

315

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

317

disp_dlg_regs->ref_freq_to_pix_freq = (dml_uint_t)(ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

318

temp = dml_pow(2, 8);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

411

disp_dlg_regs->min_dst_y_next_start = (dml_uint_t)((dml_float_t) min_dst_y_next_start * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

412

ASSERT(disp_dlg_regs->min_dst_y_next_start < (dml_uint_t)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

416

disp_dlg_regs->dst_y_prefetch = (dml_uint_t)(dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

417

disp_dlg_regs->dst_y_per_vm_vblank = (dml_uint_t)(dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

418

disp_dlg_regs->dst_y_per_row_vblank = (dml_uint_t)(dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

419

disp_dlg_regs->dst_y_per_vm_flip = (dml_uint_t)(dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

420

disp_dlg_regs->dst_y_per_row_flip = (dml_uint_t)(dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

422

disp_dlg_regs->vratio_prefetch = (dml_uint_t)(vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

423

disp_dlg_regs->vratio_prefetch_c = (dml_uint_t)(vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

432

disp_dlg_regs->refcyc_per_vm_req_vblank = (dml_uint_t)(dml_get_refcyc_per_vm_req_vblank_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

433

disp_dlg_regs->refcyc_per_vm_req_flip = (dml_uint_t)(dml_get_refcyc_per_vm_req_flip_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

454

disp_dlg_regs->dst_y_per_pte_row_nom_l = (dml_uint_t)(dst_y_per_pte_row_nom_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

455

disp_dlg_regs->dst_y_per_pte_row_nom_c = (dml_uint_t)(dst_y_per_pte_row_nom_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

456

disp_dlg_regs->dst_y_per_meta_row_nom_l = (dml_uint_t)(dst_y_per_meta_row_nom_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

457

disp_dlg_regs->dst_y_per_meta_row_nom_c = (dml_uint_t)(dst_y_per_meta_row_nom_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

482

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (dml_uint_t)(refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

483

disp_ttu_regs->refcyc_per_req_delivery_l = (dml_uint_t)(refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

484

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (dml_uint_t)(refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

485

disp_ttu_regs->refcyc_per_req_delivery_c = (dml_uint_t)(refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

486

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (dml_uint_t)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

487

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (dml_uint_t)(refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

504

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

505

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

506

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

507

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

508

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

509

disp_dlg_regs->refcyc_per_vm_group_vblank = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

511

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

512

disp_dlg_regs->refcyc_per_vm_group_flip = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

514

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

515

disp_dlg_regs->refcyc_per_vm_req_vblank = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

517

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

518

disp_dlg_regs->refcyc_per_vm_req_flip = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

522

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

523

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (dml_uint_t)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

525

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (dml_uint_t)dml_pow(2, 17)) { // FIXME what so special about chroma, can we just assert?

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

526

dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n", __func__, disp_dlg_regs->dst_y_per_pte_row_nom_c, (dml_uint_t)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

529

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (dml_uint_t)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

530

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (dml_uint_t)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

532

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

533

disp_dlg_regs->refcyc_per_pte_group_nom_l = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

535

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

536

disp_dlg_regs->refcyc_per_pte_group_nom_c = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

538

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

540

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

543

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

544

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

546

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

547

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

549

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

550

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

551

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

552

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

553

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

554

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

555

ASSERT(disp_ttu_regs->qos_level_low_wm < (dml_uint_t) dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

556

ASSERT(disp_ttu_regs->qos_level_high_wm < (dml_uint_t) dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

557

ASSERT(disp_ttu_regs->min_ttu_vblank < (dml_uint_t) dml_pow(2, 24));