drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1769

struct dml2_hubp_pipe_mcache_regs *mcache_regs)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2051

struct dml2_hubp_pipe_mcache_regs *mcache_regs = params->program_mcache_id_and_split_coordinate.mcache_regs;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

394

sizeof(struct dml2_hubp_pipe_mcache_regs));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

408

sizeof(struct dml2_hubp_pipe_mcache_regs));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

731

struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

734

struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

1025

memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct dml2_hubp_pipe_mcache_regs *));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c

630

static void reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

692

struct dml2_hubp_pipe_mcache_regs *mcache_regs)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

305

struct dml2_hubp_pipe_mcache_regs *mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1692

struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

174

struct dml2_hubp_pipe_mcache_regs *mcache_regs;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

493

struct dml2_hubp_pipe_mcache_regs mcache_regs;

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

292

void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);