drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

734

memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

211

memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

271

memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1015

struct dml2_dml_to_dc_pipe_mapping *mapping,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1035

bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

179

static bool validate_pipe_assignment(const struct dml2_context *ctx, const struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, const struct dml2_dml_to_dc_pipe_mapping *mapping)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

794

struct dml2_dml_to_dc_pipe_mapping *mapping,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

82

static int find_disp_cfg_idx_by_plane_id(struct dml2_dml_to_dc_pipe_mapping *mapping, unsigned int plane_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

852

struct dml2_dml_to_dc_pipe_mapping *mapping,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

923

struct dml2_dml_to_dc_pipe_mapping *mapping,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

941

struct dml2_dml_to_dc_pipe_mapping *mapping,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

95

static int find_disp_cfg_idx_by_stream_id(struct dml2_dml_to_dc_pipe_mapping *mapping, unsigned int stream_id)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h

33

struct dml2_dml_to_dc_pipe_mapping;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h

50

bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

101

struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h

152

struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

1200

struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

172

memset(&s_global->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c

279

memset(&s->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));