drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2963

struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2995

struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3807

struct dml2_dchub_per_pipe_register_set *hubp_regs,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3853

struct dml2_dchub_per_pipe_register_set *hubp_regs)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

221

memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c

225

memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

242

struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

248

struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

441

struct dml2_dchub_per_pipe_register_set pipe_regs[DML2_MAX_PLANES];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

339

memset(programming->plane_programming[plane_index].pipe_regs[pipe_offset], 0, sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

393

memset(programming->plane_programming[main_plane_index].phantom_plane.pipe_regs[pipe_offset], 0, sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c

608

memset(in_out->programming->plane_programming[plane_index].pipe_regs[pipe_offset], 0, sizeof(struct dml2_dchub_per_pipe_register_set));

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12750

struct dml2_dchub_per_pipe_register_set *out, int pipe_index)

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h

13

struct dml2_dchub_per_pipe_register_set;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h

23

void dml2_core_calcs_get_pipe_regs(const struct dml2_display_cfg *dml2_display_cfg, struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_per_pipe_register_set *out, int pipe_index);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

348

struct dml2_dchub_per_pipe_register_set *pipe_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

362

struct dml2_dchub_per_pipe_register_set *pipe_regs)

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

263

struct dml2_dchub_per_pipe_register_set *pipe_regs,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h

269

struct dml2_dchub_per_pipe_register_set *pipe_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1918

struct dml2_dchub_per_pipe_register_set *hubp_regs,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1935

struct dml2_dchub_per_pipe_register_set *hubp_regs);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

643

struct dml2_dchub_per_pipe_register_set *hubp_regs;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

663

struct dml2_dchub_per_pipe_register_set *hubp_regs;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

492

struct dml2_dchub_per_pipe_register_set hubp_regs;

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

168

struct dml2_dchub_per_pipe_register_set *pipe_regs,

drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h

179

struct dml2_dchub_per_pipe_register_set *pipe_regs);