drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

467

struct dmcu_firmware_header_v1_0 dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1251

struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1350

if (dmcu)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1351

hw_params.psp_version = dmcu->psp_version;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1390

if (dmcu && abm) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1391

dmcu->funcs->dmcu_init(dmcu);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1392

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2725

struct dmcu *dmcu = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2727

dmcu = adev->dm.dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2747

if (dmcu) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2748

if (!dmcu_load_iram(dmcu, params))

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

237

struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

270

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

271

dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

114

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

116

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

129

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

154

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

156

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

76

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

129

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

137

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

139

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

229

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

336

dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

338

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

143

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

246

dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

248

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

147

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

155

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

157

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

206

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

317

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

319

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

633

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

838

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

840

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1086

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1207

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1209

block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

752

params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

753

params->update_psr_wait_loop_params.dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

71

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

1528

if (dc->res_pool->dmcu != NULL)

drivers/gpu/drm/amd/display/dc/core/dc.c

1529

dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;

drivers/gpu/drm/amd/display/dc/core/dc.c

5600

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

5602

if (dmcu)

drivers/gpu/drm/amd/display/dc/core/dc.c

5603

return dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/core/dc.c

583

dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/core/dc.c

587

dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);

drivers/gpu/drm/amd/display/dc/core/dc.c

589

dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);

drivers/gpu/drm/amd/display/dc/core/dc.c

596

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

616

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

623

else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/core/dc.c

624

dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);

drivers/gpu/drm/amd/display/dc/dc.h

794

bool dmcu: 1;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

35

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

37

if (dmcu &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

38

dmcu->funcs->is_dmcu_initialized(dmcu) &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

39

dmcu->funcs->send_edid_cea) {

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

40

return dmcu->funcs->send_edid_cea(dmcu,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

52

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

54

if (dmcu &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

55

dmcu->funcs->is_dmcu_initialized(dmcu) &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

56

dmcu->funcs->recv_edid_cea_ack) {

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

57

return dmcu->funcs->recv_edid_cea_ack(dmcu, offset);

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

68

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

70

if (dmcu &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

71

dmcu->funcs->is_dmcu_initialized(dmcu) &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

72

dmcu->funcs->recv_amd_vsdb) {

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

73

return dmcu->funcs->recv_amd_vsdb(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

254

struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

282

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

283

dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

294

struct dmcu *dmcu = core_dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

332

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c

334

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1001

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

106

static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1075

struct dmcu *base = &dmcu_dce->base;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

108

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1102

struct dmcu *dce_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1123

struct dmcu *dcn10_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1144

struct dmcu *dcn20_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1165

struct dmcu *dcn21_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1186

void dce_dmcu_destroy(struct dmcu **dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1188

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1191

*dmcu = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

129

static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

131

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

155

dce_get_dmcu_psr_state(dmcu, &state);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

168

static bool dce_dmcu_setup_psr(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

172

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

250

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

262

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

267

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

280

static bool dce_is_dmcu_initialized(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

282

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

296

struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

299

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

302

if (dmcu->cached_wait_loop_number == wait_loop_number)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

306

if (!dce_is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

314

dmcu->cached_wait_loop_number = wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

315

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

325

struct dmcu *dmcu, unsigned int *psr_wait_loop_number)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

327

*psr_wait_loop_number = dmcu->cached_wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

331

static void dcn10_get_dmcu_version(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

333

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

34

#define TO_DCE_DMCU(dmcu)\

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

345

dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

346

dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

347

dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

348

dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

35

container_of(dmcu, struct dce_dmcu, base)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

357

static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

360

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

379

static bool dcn10_dmcu_init(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

381

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

382

const struct dc_config *config = &dmcu->ctx->dc->config;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

384

struct dc_context *ctx = dmcu->ctx;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

396

dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

407

switch (dmcu->dmcu_state) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

434

dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

437

if (dmcu->dmcu_state == DMCU_RUNNING) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

439

dcn10_get_dmcu_version(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

442

dcn10_dmcu_enable_fractional_pwm(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

462

static bool dcn21_dmcu_init(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

464

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

467

if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

471

return dcn10_dmcu_init(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

474

static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

479

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

483

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

519

static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

521

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

526

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

546

static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

548

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

556

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

581

dcn10_get_dmcu_psr_state(dmcu, &state);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

599

static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

603

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

613

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

689

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

701

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

706

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

72

static bool dce_dmcu_init(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

724

struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

727

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

731

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

740

dmcu->cached_wait_loop_number = wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

741

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

752

struct dmcu *dmcu, unsigned int *psr_wait_loop_number)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

754

*psr_wait_loop_number = dmcu->cached_wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

758

static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

761

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

768

static bool dcn20_lock_phy(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

770

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

773

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

78

static bool dce_dmcu_load_iram(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

791

static bool dcn20_unlock_phy(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

793

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

796

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

814

static bool dcn10_send_edid_cea(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

820

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

824

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

83

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

855

static bool dcn10_get_scp_results(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

861

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

864

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

878

static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

886

if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3]))

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

906

static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

911

if (!dcn10_get_scp_results(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

930

static void dcn10_forward_crc_window(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

934

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

941

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

963

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

966

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

969

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

980

static void dcn10_stop_crc_win_update(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

983

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

989

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

234

struct dmcu base;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

305

struct dmcu *dce_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

311

struct dmcu *dcn10_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

317

struct dmcu *dcn20_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

323

struct dmcu *dcn21_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

329

void dce_dmcu_destroy(struct dmcu **dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2808

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2871

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2872

if (dmcu != NULL && abm != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2873

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3187

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3197

if (dmcu)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3198

fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3281

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3325

if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3326

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3334

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3335

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3346

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3352

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3353

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3362

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3363

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1764

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1876

if (dmcu != NULL && !dmcu->auto_load_dmcu)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1877

dmcu->funcs->dmcu_init(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1880

if (abm != NULL && dmcu != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1881

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

183

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

191

if (dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

216

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

224

if (dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

259

if (dc->dc->res_pool->dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

664

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

77

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

510

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

516

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

517

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

526

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

527

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1408

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1414

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1415

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1424

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1425

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1756

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1762

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1763

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1777

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1778

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

83

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1054

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1060

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1061

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1075

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1076

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

321

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

60

bool (*dmcu_init)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

61

bool (*load_iram)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

65

void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

66

bool (*setup_psr)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

69

void (*get_psr_state)(struct dmcu *dmcu, enum dc_psr_state *dc_psr_state);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

70

void (*set_psr_wait_loop)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

72

void (*get_psr_wait_loop)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

74

bool (*is_dmcu_initialized)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

75

bool (*lock_phy)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

76

bool (*unlock_phy)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

77

bool (*send_edid_cea)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

82

bool (*recv_amd_vsdb)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

86

bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

88

void (*forward_crc_window)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

91

void (*stop_crc_win_update)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1212

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1215

if (dmcu)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1216

fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

588

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

624

} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

626

dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

636

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

645

else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

646

dmcu->funcs->get_psr_state(dmcu, state);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

693

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

733

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

736

if (!dmcu && !psr)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

895

link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1083

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1087

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

840

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

841

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1419

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1423

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

877

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

878

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1305

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1309

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

842

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

843

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1140

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1144

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

664

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

665

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1180

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1184

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1377

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1381

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

876

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

877

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

982

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

986

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1193

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1197

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1391

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1395

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

882

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

883

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

993

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

997

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1007

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1008

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1481

pool->base.dmcu = dcn10_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1485

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1215

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1216

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2570

pool->base.dmcu = dcn20_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2574

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1545

pool->base.dmcu = dcn21_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1549

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

782

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

783

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

897

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

917

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

897

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

892

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

725

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

721

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

755

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

735

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

742

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

719

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

766

bool dmcu_load_iram(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

772

if (dmcu == NULL)

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

775

if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

780

if (dmcu->dmcu_version.abm_version == 0x24) {

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

782

result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

784

} else if (dmcu->dmcu_version.abm_version == 0x23) {

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

787

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

788

dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

789

} else if (dmcu->dmcu_version.abm_version == 0x22) {

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

792

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

793

dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

797

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

798

dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

801

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_helpers.c

802

dmcu, IRAM_RESERVE_AREA_END_V2 + 1,

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

50

bool dmcu_load_iram(struct dmcu *dmcu,