drivers/gpu/drm/i915/display/intel_dmc.c

1009

if (dmc->dmc_info[dmc_id].present)

drivers/gpu/drm/i915/display/intel_dmc.c

1013

dmc->dmc_info[dmc_id].present = true;

drivers/gpu/drm/i915/display/intel_dmc.c

1014

dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset;

drivers/gpu/drm/i915/display/intel_dmc.c

1057

struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];

drivers/gpu/drm/i915/display/intel_dmc.c

1063

BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||

drivers/gpu/drm/i915/display/intel_dmc.c

1064

ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);

drivers/gpu/drm/i915/display/intel_dmc.c

1129

dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);

drivers/gpu/drm/i915/display/intel_dmc.c

1130

dmc_info->mmiodata[i] = mmiodata[i];

drivers/gpu/drm/i915/display/intel_dmc.c

1135

dmc_info->mmiodata[i],

drivers/gpu/drm/i915/display/intel_dmc.c

1136

dmc_info->mmiodata[i+1],

drivers/gpu/drm/i915/display/intel_dmc.c

1140

dmc_info->mmioaddr[i], &dmc_info->mmiodata[i],

drivers/gpu/drm/i915/display/intel_dmc.c

1141

dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1]))

drivers/gpu/drm/i915/display/intel_dmc.c

1146

i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]),

drivers/gpu/drm/i915/display/intel_dmc.c

1147

orig_mmiodata[0], dmc_info->mmiodata[i]);

drivers/gpu/drm/i915/display/intel_dmc.c

1150

i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]),

drivers/gpu/drm/i915/display/intel_dmc.c

1151

orig_mmiodata[1], dmc_info->mmiodata[i+1]);

drivers/gpu/drm/i915/display/intel_dmc.c

1156

i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i],

drivers/gpu/drm/i915/display/intel_dmc.c

1157

is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :

drivers/gpu/drm/i915/display/intel_dmc.c

1158

is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",

drivers/gpu/drm/i915/display/intel_dmc.c

1159

disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i],

drivers/gpu/drm/i915/display/intel_dmc.c

1160

dmc_info->mmiodata[i]) ? " (disabling)" : "");

drivers/gpu/drm/i915/display/intel_dmc.c

1162

dmc_info->mmio_count = mmio_count;

drivers/gpu/drm/i915/display/intel_dmc.c

1163

dmc_info->start_mmioaddr = start_mmioaddr;

drivers/gpu/drm/i915/display/intel_dmc.c

1176

dmc_info->dmc_fw_size = dmc_header->fw_size;

drivers/gpu/drm/i915/display/intel_dmc.c

1178

dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);

drivers/gpu/drm/i915/display/intel_dmc.c

1179

if (!dmc_info->payload)

drivers/gpu/drm/i915/display/intel_dmc.c

1183

memcpy(dmc_info->payload, payload, payload_size);

drivers/gpu/drm/i915/display/intel_dmc.c

1304

if (!dmc->dmc_info[dmc_id].present)

drivers/gpu/drm/i915/display/intel_dmc.c

1307

offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;

drivers/gpu/drm/i915/display/intel_dmc.c

1529

kfree(dmc->dmc_info[dmc_id].payload);

drivers/gpu/drm/i915/display/intel_dmc.c

1676

intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

drivers/gpu/drm/i915/display/intel_dmc.c

1763

return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0;

drivers/gpu/drm/i915/display/intel_dmc.c

414

return dmc && dmc->dmc_info[dmc_id].payload;

drivers/gpu/drm/i915/display/intel_dmc.c

640

dmc->dmc_info[dmc_id].mmioaddr[i],

drivers/gpu/drm/i915/display/intel_dmc.c

641

dmc->dmc_info[dmc_id].mmiodata[i]))

drivers/gpu/drm/i915/display/intel_dmc.c

642

return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]);

drivers/gpu/drm/i915/display/intel_dmc.c

644

return dmc->dmc_info[dmc_id].mmiodata[i];

drivers/gpu/drm/i915/display/intel_dmc.c

652

for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {

drivers/gpu/drm/i915/display/intel_dmc.c

653

intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i],

drivers/gpu/drm/i915/display/intel_dmc.c

667

for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {

drivers/gpu/drm/i915/display/intel_dmc.c

669

DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),

drivers/gpu/drm/i915/display/intel_dmc.c

670

dmc->dmc_info[dmc_id].payload[i]);

drivers/gpu/drm/i915/display/intel_dmc.c

688

found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0));

drivers/gpu/drm/i915/display/intel_dmc.c

689

expected = dmc->dmc_info[dmc_id].payload[0];

drivers/gpu/drm/i915/display/intel_dmc.c

695

for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {

drivers/gpu/drm/i915/display/intel_dmc.c

696

i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];

drivers/gpu/drm/i915/display/intel_dmc.c

83

} dmc_info[DMC_FW_MAX];

drivers/gpu/drm/i915/display/intel_dmc.c

846

for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {

drivers/gpu/drm/i915/display/intel_dmc.c

847

i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i];

drivers/gpu/drm/i915/display/intel_dmc.c

848

u32 data = dmc->dmc_info[dmc_id].mmiodata[i];

drivers/perf/amlogic/meson_ddr_pmu_core.c

22

struct dmc_info info;

drivers/perf/amlogic/meson_ddr_pmu_core.c

349

struct dmc_info *info = dev_id;

drivers/perf/amlogic/meson_ddr_pmu_core.c

444

struct dmc_info *info)

drivers/perf/amlogic/meson_g12_ddr_pmu.c

128

static unsigned long dmc_g12_get_freq_quick(struct dmc_info *info)

drivers/perf/amlogic/meson_g12_ddr_pmu.c

173

static void g12_dump_reg(struct dmc_info *db)

drivers/perf/amlogic/meson_g12_ddr_pmu.c

199

static void dmc_g12_counter_enable(struct dmc_info *info)

drivers/perf/amlogic/meson_g12_ddr_pmu.c

220

static void dmc_g12_config_fiter(struct dmc_info *info,

drivers/perf/amlogic/meson_g12_ddr_pmu.c

255

static void dmc_g12_set_axi_filter(struct dmc_info *info, int axi_id, int channel)

drivers/perf/amlogic/meson_g12_ddr_pmu.c

263

static void dmc_g12_counter_disable(struct dmc_info *info)

drivers/perf/amlogic/meson_g12_ddr_pmu.c

283

static void dmc_g12_get_counters(struct dmc_info *info,

drivers/perf/amlogic/meson_g12_ddr_pmu.c

298

static int dmc_g12_irq_handler(struct dmc_info *info,

include/soc/amlogic/meson_ddr_pmu.h

24

struct dmc_info;

include/soc/amlogic/meson_ddr_pmu.h

39

void (*enable)(struct dmc_info *info);

include/soc/amlogic/meson_ddr_pmu.h

40

void (*disable)(struct dmc_info *info);

include/soc/amlogic/meson_ddr_pmu.h

42

void (*set_axi_filter)(struct dmc_info *info, int axi_id, int chann);

include/soc/amlogic/meson_ddr_pmu.h

43

int (*irq_handler)(struct dmc_info *info,

include/soc/amlogic/meson_ddr_pmu.h

45

void (*get_counters)(struct dmc_info *info,