dmar_writeq
dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob);
dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT));
dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
dmar_writeq(iommu->reg + tlb_offset, val_iva);
dmar_writeq(iommu->reg + tlb_offset + 8, val);
dmar_writeq(iommu->reg + DMAR_IRTA_REG,
dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config);
dmar_writeq(iommu_pmu->overflow, status);
dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);