dmar_readq
value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)
dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG +
u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);
iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);
guest_addr = dmar_readq(iommu->reg + reg +
cap = dmar_readq(addr + DMAR_CAP_REG);
ecap = dmar_readq(addr + DMAR_ECAP_REG);
iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
res = dmar_readq(iommu->reg + DMAR_ECRSP_REG);
IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq,
dmar_readq, (!(val & DMA_CCMD_ICC)), val);
dmar_readq, (!(val & DMA_TLB_IVT)), val);
irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
new_count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx));
count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx));
while ((status = dmar_readq(iommu_pmu->overflow))) {
perfcap = dmar_readq(iommu->reg + DMAR_PERFCAP_REG);
pcap = dmar_readq(iommu->reg + DMAR_PERFEVNTCAP_REG +
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;