dma_writel
dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
dma_writel(atdma, EN, 0);
dma_writel(atdma, EBCIDR, -1L);
dma_writel(atdma, EN, AT_DMA_ENABLE);
dma_writel(atdma, CHER, atchan->mask);
dma_writel(atdma, EN, AT_DMA_ENABLE);
dma_writel(atdma, EBCIER, atdma->save_imr);
dma_writel(atdma, EBCIER, ebci);
dma_writel(atdma, EBCIDR, ebci);
dma_writel(atchan->atdma, CHER, atchan->mask);
dma_writel(atchan->atdma, CHDR, AT_DMA_RES(i) | atchan->mask);
dma_writel(dw, CFG, 0);
dma_writel(dw, CFG, DW_CFG_DMA_EN);
dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
dma_writel(dw, CLEAR.XFER, dwc->mask);
dma_writel(dw, CLEAR.ERROR, dwc->mask);
dma_writel(dw, reg, ((mask) << 8) | (mask))
dma_writel(dw, reg, ((mask) << 8) | 0)
dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
dma_writel(idma64, CLEAR(XFER), idma64c->mask);
dma_writel(idma64, CFG, 0);
dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
dma_writel(idma64, reg, ((mask) << 8) | (mask))
dma_writel(idma64, reg, ((mask) << 8) | 0)
dma_writel(od, OWL_DMA_IRQ_EN0, 0x0);
dma_writel(od, OWL_DMA_IRQ_PD0, (1 << pchan->id));
dma_writel(od, OWL_DMA_IRQ_PD0, pending);
dma_writel(pd, CTL2, val);
dma_writel(pd, CTL0, val);
dma_writel(pd, CTL3, val);
dma_writel(pd, CTL0, val);
dma_writel(pd, CTL3, val);
dma_writel(pd, STS0, sts0);
dma_writel(pd, STS2, sts2);
dma_writel(pd, CTL0, pd->regs.dma_ctl0);
dma_writel(pd, CTL1, pd->regs.dma_ctl1);
dma_writel(pd, CTL2, pd->regs.dma_ctl2);
dma_writel(pd, CTL3, pd->regs.dma_ctl3);
dma_writel(ddev, MCR, 0);
dma_writel(ddev, MCR, mcr);
dma_writel(ddev, MCR, mcr);