dma_reg
struct dma_reg ch[DMA_CHAN_COUNT];
static inline int rc32434_halt_dma(struct dma_reg *ch)
static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
struct dma_regs *dma_reg;
dma_reg = chan->device->dma_reg;
if (ioread16(&dma_reg->cpfhp) != ioread16(&dma_reg->cpftp) ||
ioread16(&dma_reg->cpftp) != ioread16(&dma_reg->csftp))
struct dma_regs *dma_reg = chan->device->dma_reg;
iowrite32(pcdb, &dma_reg->cpfpl);
struct dma_regs *dma_reg;
dma_reg = chan->device->dma_reg;
return ioread32(&dma_reg->acpl) & (~DMA_CDB_MSK);
adev->dma_reg = regs;
&adev->dma_reg->fsiz);
&adev->dma_reg->cfg);
iowrite32(~0, &adev->dma_reg->dsts);
iounmap(adev->dma_reg);
iounmap(adev->dma_reg);
struct dma_regs *dma_reg;
dma_reg = chan->device->dma_reg;
while ((rv = ioread32(&dma_reg->csfpl))) {
rv = ioread32(&dma_reg->dsts);
iowrite32(rv, &dma_reg->dsts);
struct dma_regs __iomem *dma_reg;
dma_reg = &pdcs->regs->dmaregs[ringset];
iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
&dma_reg->dmarcv.control);
iowrite32(0, &dma_reg->dmaxmt.ptr);
iowrite32(0, &dma_reg->dmarcv.ptr);
&dma_reg->dmaxmt.addrlow);
&dma_reg->dmaxmt.addrhigh);
&dma_reg->dmarcv.addrlow);
&dma_reg->dmarcv.addrhigh);
iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control);
&dma_reg->dmarcv.control);
struct dma64 *dma_reg;
dma_reg = &pdcs->regs->dmaregs[ringset];
iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
&dma_reg->dmarcv.control);
iowrite32(0, &dma_reg->dmaxmt.ptr);
iowrite32(0, &dma_reg->dmarcv.ptr);
struct dma64 *dma_reg;
dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET];
iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);
&dma_reg->dmarcv.control);
struct dma64 *dma_reg;
enum flash_dma_reg dma_reg, u32 val)
u16 offs = ctrl->flash_dma_offsets[dma_reg];
enum flash_dma_reg dma_reg)
u16 offs = ctrl->flash_dma_offsets[dma_reg];
dma_reg |= R852_DMA_INTERNAL;
dma_reg |= R852_DMA_MEMORY;
r852_write_reg_dword(dev, R852_DMA_SETTINGS, dma_reg);
uint8_t dma_reg, dma_irq_reg;
dma_reg = r852_read_reg_dword(dev, R852_DMA_SETTINGS);
dma_reg &= ~(R852_DMA_READ | R852_DMA_INTERNAL | R852_DMA_MEMORY);
dma_reg |= R852_DMA_READ;
u32 dma_reg, fl_reg, bch_reg;
dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) |
writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off);
enum dma_reg r)
u32 val, enum dma_reg r)
enum dma_reg r)
u32 val, enum dma_reg r)
void __iomem *dma_reg;
dma_reg = &qhdr->word0;
writel(0, dma_reg);
tx_crq.v1.dma_reg = cpu_to_be16(ltb->map_id);
__be16 dma_reg;
struct dma_reg __iomem *rx_dma_regs;
struct dma_reg __iomem *tx_dma_regs;
struct dma_reg *ch)
qla2xxx_read_window(reg, 48, fw->dma_reg);
for (cnt = 0; cnt < ARRAY_SIZE(fw->dma_reg); cnt++, dmp_reg++)
fw->dma_reg[cnt] = htons(rd_reg_word(dmp_reg));
__be16 dma_reg[48];
__be16 dma_reg[48];
dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
unsigned int dma_reg;
dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
__func__, (u32)hs_ep->desc_list_dma, dma_reg);
dwc2_writel(hsotg, ureq->dma, dma_reg);
__func__, &ureq->dma, dma_reg);
u32 dma_reg;
u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
dma_reg |= I2S_DMAEN_TXBLOCK;
dma_reg |= I2S_DMAEN_RXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
dma_reg &= ~I2S_DMAEN_TXBLOCK;
dma_reg &= ~I2S_DMAEN_RXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
u32 dma_reg;
dma_reg = readl(kmb_i2s->i2s_base + I2S_DMACR);
dma_reg |= I2S_DMAEN_TXBLOCK;
dma_reg |= I2S_DMAEN_RXBLOCK;
writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR);
u32 dma_reg;
dma_reg = readl(kmb_i2s->i2s_base + I2S_DMACR);
dma_reg &= ~I2S_DMAEN_TXBLOCK;
dma_reg &= ~I2S_DMAEN_RXBLOCK;
writel(dma_reg, kmb_i2s->i2s_base + I2S_DMACR);