dma_fence_init
dma_fence_init(&fence->base, &fence_ops, &fence->lock, hwctx->id, 0);
dma_fence_init(fence, ðosu_fence_ops, &dev->fence_lock,
dma_fence_init(&fence->base, &ivpu_fence_ops, &fence->lock, dma_fence_context_alloc(1), 1);
dma_fence_init(fence, &rocket_fence_ops, &core->fence_lock,
dma_fence_init(&array->base, &dma_fence_array_ops, &array->lock,
EXPORT_SYMBOL(dma_fence_init);
dma_fence_init(&dma_fence_stub, &dma_fence_stub_ops,
dma_fence_init(fence,
dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0);
dma_fence_init(&f->base, &mock_ops, &f->lock, context, seqno);
dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0);
dma_fence_init(f, &fence_ops, &fence_lock, 0, 0);
dma_fence_init(&pt->base, &timeline_fence_ops, &obj->lock,
dma_fence_init(&fence->base, &amdkfd_fence_ops, &fence->lock,
dma_fence_init(fence, &amdgpu_fence_ops,
dma_fence_init(fence, &drm_crtc_fence_ops, &crtc->fence_lock,
dma_fence_init(fence, &drm_writeback_fence_ops,
dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
dma_fence_init(&work->fence, &dma_fence_memcpy_ops, &work->lock, 0, 0);
dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
dma_fence_init(&f->dma, &fence_ops, &f->lock, 0, 0);
dma_fence_init(&vma_res->unbind_fence, &unbind_fence_ops,
dma_fence_init(dma, &mock_fence_ops, &mock_fence_lock, 0, 0);
dma_fence_init(&fence->base, &pvr_kccb_fence_ops,
dma_fence_init(&fence->base, fence_ops,
dma_fence_init(&fence->base, &lima_fence_ops, &pipe->fence_lock,
dma_fence_init(&f->base, &msm_fence_ops, &fctx->spinlock,
dma_fence_init(&fence->base, &nouveau_fence_ops_uevent,
dma_fence_init(&fence->base, &nouveau_fence_ops_legacy,
dma_fence_init(&fence->base, &panfrost_fence_ops, &js->job_lock,
dma_fence_init(job->done_fence,
dma_fence_init(&release->base, &qxl_fence_ops, &qdev->release_lock,
dma_fence_init(&(*fence)->base, &radeon_fence_ops,
dma_fence_init(&fence->scheduled, &drm_sched_fence_ops_scheduled,
dma_fence_init(&fence->finished, &drm_sched_fence_ops_finished,
dma_fence_init(&job->hw_fence,
dma_fence_init(fence, &mock_fence_ops, &fence_lock, 0, 0);
dma_fence_init(fence, &fence_ops, &fence_lock, 0, 0);
dma_fence_init(&fence->base, &v3d_fence_ops, &queue->fence_lock,
dma_fence_init(&fence->base, &vc4_fence_ops, &vc4->job_lock,
dma_fence_init(&fence->base, &vgem_fence_ops, &fence->lock,
dma_fence_init(&fence->f, &virtio_gpu_fence_ops, &drv->lock,
dma_fence_init(&fence->base, &vmw_fence_ops, &fman->lock,
dma_fence_init(fence, &xe_hw_fence_ops, &ctx->irq->lock,
dma_fence_init(&ofence->base, &xe_oa_fence_ops, &ofence->lock, 0, 0);
dma_fence_init(&pfence->base, &preempt_fence_ops,
dma_fence_init(&fence->base, &inval_fence_ops, &tlb_inval->lock,
dma_fence_init(&fence->base, &host1x_syncpt_fence_ops, &sp->fences.lock,
dma_fence_init(&fence->base, &iio_buffer_dma_fence_ops,
dma_fence_init(&fence->base, &ffs_dmabuf_fence_ops,
void dma_fence_init(struct dma_fence *fence, const struct dma_fence_ops *ops,
DEFINE_EVENT(dma_fence_unsignaled, dma_fence_init,