dma_ctrl_write
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);
dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),
dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);
dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);
dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);
dma_ctrl_write(chan, reg, addr);
MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);