dma_base_addr
u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR);
__raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR));
__raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR));
__raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR));
(dma_base_addr(chan->chan) + TCR));
if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE))
return __raw_readl(dma_base_addr(chan->chan) + TCR)
void __iomem *dma_base_addr;
dma_base_addr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dma_base_addr))
return PTR_ERR(dma_base_addr);
ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
u32 dma_no, dma_base_addr, temp_addr;
dma_base_addr = QLC_DMA_REG_BASE_ADDR(dma_no);
temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_LOW;
temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_HI;
temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL;
temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL;
u32 temp, dma_base_addr, size = 0, read_size = 0;
dma_base_addr = QLC_DMA_REG_BASE_ADDR(temp);
dma_base_addr + QLC_DMA_CMD_STATUS_CTRL);
uint64_t dma_base_addr = 0;
dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
(dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
uint64_t dma_base_addr = 0;
dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
(dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
uint64_t dma_base_addr = 0;
dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
(dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),
uint64_t dma_base_addr = 0;
dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS +
dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW,
dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0);
dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL,
(dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL),