dm9051_set_reg
return dm9051_set_reg(db, DM9051_FCR, fcr);
return dm9051_set_reg(db, DM9051_RCR, db->rctl.rcr_all); /* enable rx */
return dm9051_set_reg(db, DM9051_INTCR, dm9051_intcr_value(db));
return dm9051_set_reg(db, DM9051_IMR, IMR_PAR); /* disable int */
return dm9051_set_reg(db, DM9051_IMR, db->imr_all); /* enable int */
return dm9051_set_reg(db, DM9051_ISR, ISR_STOP_MRCMD); /* to stop mrcmd */
ret = dm9051_set_reg(db, DM9051_GPR, 0);
ret = dm9051_set_reg(db, DM9051_GPR, GPR_PHY_OFF);
return dm9051_set_reg(db, DM9051_RCR, RCR_RX_DISABLE);
return dm9051_set_reg(db, DM9051_TCR, TCR_TXREQ);