drivers/gpu/drm/lima/lima_dlbu.c

27

dlbu_write(LIMA_DLBU_PP_ENABLE_MASK, mask);

drivers/gpu/drm/lima/lima_dlbu.c

34

dlbu_write(LIMA_DLBU_PP_ENABLE_MASK, 0);

drivers/gpu/drm/lima/lima_dlbu.c

39

dlbu_write(LIMA_DLBU_TLLIST_VBASEADDR, reg[0]);

drivers/gpu/drm/lima/lima_dlbu.c

40

dlbu_write(LIMA_DLBU_FB_DIM, reg[1]);

drivers/gpu/drm/lima/lima_dlbu.c

41

dlbu_write(LIMA_DLBU_TLLIST_CONF, reg[2]);

drivers/gpu/drm/lima/lima_dlbu.c

42

dlbu_write(LIMA_DLBU_START_TILE_POS, reg[3]);

drivers/gpu/drm/lima/lima_dlbu.c

49

dlbu_write(LIMA_DLBU_MASTER_TLLIST_PHYS_ADDR, dev->dlbu_dma | 1);

drivers/gpu/drm/lima/lima_dlbu.c

50

dlbu_write(LIMA_DLBU_MASTER_TLLIST_VADDR, LIMA_VA_RESERVE_DLBU);