drivers/clk/stm32/clk-stm32-core.c

212

const struct stm32_div_cfg *divider = &data->dividers[div_id];

drivers/clk/stm32/clk-stm32-core.c

235

const struct stm32_div_cfg *divider = &data->dividers[div_id];

drivers/clk/stm32/clk-stm32-core.c

363

divider = &div->clock_data->dividers[div->div_id];

drivers/clk/stm32/clk-stm32-core.c

440

divider = &composite->clock_data->dividers[composite->div_id];

drivers/clk/stm32/clk-stm32-core.h

63

const struct stm32_div_cfg *dividers;

drivers/clk/stm32/clk-stm32mp13.c

1512

.dividers = stm32mp13_dividers,

drivers/clk/ti/clk-44xx.c

661

.dividers = omap4_trace_clk_div_div_ck_divs,

drivers/clk/ti/clkctrl.c

409

if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,

drivers/clk/ti/clock.h

120

int *dividers;

drivers/clk/ti/clock.h

162

const int *dividers;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1019

struct atom_clock_dividers *dividers)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1026

memset(dividers, 0, sizeof(struct atom_clock_dividers));

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1044

dividers->post_div = args.v3.ucPostDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1045

dividers->enable_post_div = (args.v3.ucCntlFlag &

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1047

dividers->enable_dithen = (args.v3.ucCntlFlag &

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1049

dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1050

dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1051

dividers->ref_div = args.v3.ucRefDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1052

dividers->vco_mode = (args.v3.ucCntlFlag &

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1066

dividers->post_div = args.v5.ucPostDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1067

dividers->enable_post_div = (args.v5.ucCntlFlag &

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1069

dividers->enable_dithen = (args.v5.ucCntlFlag &

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1071

dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1072

dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1073

dividers->ref_div = args.v5.ucRefDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1074

dividers->vco_mode = (args.v5.ucCntlFlag &

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1086

dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1087

dividers->real_clock = le32_to_cpu(args.v4.ulClock);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1099

dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1100

dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1101

dividers->ref_div = args.v6_out.ucPllRefDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1102

dividers->post_div = args.v6_out.ucPllPostDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1103

dividers->flags = args.v6_out.ucPllCntlFlag;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1104

dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1105

dividers->post_divider = args.v6_out.ulClock.ucPostDiv;

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

159

struct atom_clock_dividers *dividers);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

207

struct atom_clock_dividers *dividers);

drivers/gpu/drm/amd/amdgpu/cik.c

1455

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/amdgpu/cik.c

1460

clock, false, &dividers);

drivers/gpu/drm/amd/amdgpu/cik.c

1467

tmp |= dividers.post_divider;

drivers/gpu/drm/amd/amdgpu/cik.c

1496

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/amdgpu/cik.c

1501

ecclk, false, &dividers);

drivers/gpu/drm/amd/amdgpu/cik.c

1516

tmp |= dividers.post_divider;

drivers/gpu/drm/amd/amdgpu/vi.c

1000

tmp |= dividers.post_divider;

drivers/gpu/drm/amd/amdgpu/vi.c

1054

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/amdgpu/vi.c

1075

ecclk, false, &dividers);

drivers/gpu/drm/amd/amdgpu/vi.c

1090

tmp |= dividers.post_divider;

drivers/gpu/drm/amd/amdgpu/vi.c

984

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/amdgpu/vi.c

989

clock, false, &dividers);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1277

struct dividers dividers)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1313

dividers.divider1);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1315

dividers.divider1);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1317

dividers.divider1);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1322

dividers.divider2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1324

dividers.divider2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1326

dividers.divider2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1331

dividers.divider3);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1333

dividers.divider3);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1335

dividers.divider3);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1340

struct dividers dividers)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1499

struct dividers dividers)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1522

p->r = dc_fixpt_div(p_last->r, dividers.divider1);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1523

p->g = dc_fixpt_div(p_last->g, dividers.divider1);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1524

p->b = dc_fixpt_div(p_last->b, dividers.divider1);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1528

p->r = dc_fixpt_div(p_last->r, dividers.divider2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1529

p->g = dc_fixpt_div(p_last->g, dividers.divider2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1530

p->b = dc_fixpt_div(p_last->b, dividers.divider2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1534

p->r = dc_fixpt_div(p_last->r, dividers.divider3);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1535

p->g = dc_fixpt_div(p_last->g, dividers.divider3);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1536

p->b = dc_fixpt_div(p_last->b, dividers.divider3);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1675

struct dividers dividers;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1727

dividers.divider1 = dc_fixpt_from_fraction(3, 2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1728

dividers.divider2 = dc_fixpt_from_int(2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1729

dividers.divider3 = dc_fixpt_from_fraction(5, 2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1734

dividers);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1736

scale_gamma(rgb_user, ramp, dividers);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1913

struct dividers dividers;

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1949

dividers.divider1 = dc_fixpt_from_fraction(3, 2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1950

dividers.divider2 = dc_fixpt_from_int(2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1951

dividers.divider3 = dc_fixpt_from_fraction(5, 2);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1956

dividers);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1959

scale_gamma(rgb_user, ramp, dividers);

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1961

scale_gamma_dx(rgb_user, ramp, dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1030

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1050

table->entries[i].clk, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1053

pi->samu_level[i].Divider = (u8)dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1096

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1109

table->entries[i].clk, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

1112

pi->acp_level[i].Divider = (u8)dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

655

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

659

sclk, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

663

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

896

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

919

table->entries[i].vclk, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

922

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

925

table->entries[i].dclk, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

928

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

969

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

987

table->entries[i].evclk, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

990

pi->vce_level[i].Divider = (u8)dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5327

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5341

engine_clock, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5345

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5347

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5352

spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5353

spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5364

u32 vco_freq = engine_clock * dividers.post_div;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7407

struct atom_clock_dividers dividers;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7467

0, false, &dividers);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7469

pi->ref_div = dividers.ref_div + 1;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

397

pp_atomctrl_clock_dividers_kong *dividers)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

410

dividers->pll_post_divider = pll_parameters.ucPostDiv;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

411

dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

420

pp_atomctrl_clock_dividers_vi *dividers)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

434

dividers->pll_post_divider =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

436

dividers->real_clock =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

439

dividers->ul_fb_div.ul_fb_div_frac =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

441

dividers->ul_fb_div.ul_fb_div =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

444

dividers->uc_pll_ref_div =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

446

dividers->uc_pll_post_div =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

448

dividers->uc_pll_cntl_flag =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

457

pp_atomctrl_clock_dividers_ai *dividers)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

471

dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

472

dividers->usSclk_fcw_int = le16_to_cpu(pll_patameters.usSclk_fcw_int);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

473

dividers->ucSclkPostDiv = pll_patameters.ucSclkPostDiv;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

474

dividers->ucSclkVcoMode = pll_patameters.ucSclkVcoMode;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

475

dividers->ucSclkPllRange = pll_patameters.ucSclkPllRange;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

476

dividers->ucSscEnable = pll_patameters.ucSscEnable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

477

dividers->usSsc_fcw1_frac = le16_to_cpu(pll_patameters.usSsc_fcw1_frac);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

478

dividers->usSsc_fcw1_int = le16_to_cpu(pll_patameters.usSsc_fcw1_int);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

479

dividers->usPcc_fcw_int = le16_to_cpu(pll_patameters.usPcc_fcw_int);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

480

dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

481

dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

489

pp_atomctrl_clock_dividers_vi *dividers)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

504

dividers->pll_post_divider =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

506

dividers->real_clock =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

509

dividers->ul_fb_div.ul_fb_div_frac =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

511

dividers->ul_fb_div.ul_fb_div =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

514

dividers->uc_pll_ref_div =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

516

dividers->uc_pll_post_div =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

518

dividers->uc_pll_cntl_flag =

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

306

extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

307

extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

316

pp_atomctrl_clock_dividers_kong *dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.h

319

extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

170

struct pp_atomfwctrl_clock_dividers_soc15 *dividers)

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

188

dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

189

dividers->ulDid = le32_to_cpu(pll_output->dfs_did);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

190

dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

191

dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

192

dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c

193

dividers->ucPll_ss_enable = pll_output->pll_ss_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.h

219

struct pp_atomfwctrl_clock_dividers_soc15 *dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

440

pp_atomctrl_clock_dividers_kong dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

485

&dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

488

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

502

&dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

505

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

516

&dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

519

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

528

&dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

531

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

542

&dividers);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c

545

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1502

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1507

lclock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1511

*curr_lclk_did = dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1620

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1649

gfx_clock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1655

cpu_to_le32(dividers.ulPll_fb_mult);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1657

current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1659

cpu_to_le32(dividers.ulPll_ss_fbsmult);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1661

cpu_to_le16(dividers.usPll_ss_slew_frac);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1662

current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1687

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1711

soc_clock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1715

*current_soc_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1824

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1852

hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1860

current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1861

current_memclk_level->Did = (uint8_t)(dividers.ulDid);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1996

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2001

eclock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2005

*current_eclk_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2049

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2053

vclock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2057

*current_vclk_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2065

struct pp_atomfwctrl_clock_dividers_soc15 dividers;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2069

dclock, &dividers),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

2073

*current_dclk_did = (uint8_t)dividers.ulDid;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1382

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1405

table->ACPILevel.SclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1411

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1523

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1539

table->UvdLevel[count].VclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1543

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1546

table->UvdLevel[count].DclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1550

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1564

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1578

table->VceLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1583

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1596

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1609

table->AcpLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1613

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

301

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

313

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

321

ref_divider = 1 + dividers.uc_pll_ref_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

324

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

328

SPLL_REF_DIV, dividers.uc_pll_ref_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

330

SPLL_PDIV_A, dividers.uc_pll_post_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

343

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

366

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1303

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1334

table->ACPILevel.SclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1339

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1423

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1444

table->VceLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1449

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1462

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1481

table->AcpLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1485

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1558

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1579

table->UvdLevel[count].VclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1583

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1586

table->UvdLevel[count].DclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

1590

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

859

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

871

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

879

ref_divider = 1 + dividers.uc_pll_ref_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

882

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

886

SPLL_REF_DIV, dividers.uc_pll_ref_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

888

SPLL_PDIV_A, dividers.uc_pll_post_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

902

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

931

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1427

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1451

table->ACPILevel.SclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

1457

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

799

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

811

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

819

reference_divider = 1 + dividers.uc_pll_ref_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

822

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

826

CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

828

CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

842

uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

868

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1058

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1085

&dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1091

dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1092

dividers.pll_post_divider - 1 : dividers.pll_post_divider,

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1370

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1402

table->VceLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1407

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1420

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1451

table->SamuLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1456

table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1525

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1556

table->UvdLevel[count].VclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1560

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1563

table->UvdLevel[count].DclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1567

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

1924

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2094

result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2098

table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

2100

table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

895

struct pp_atomctrl_clock_dividers_ai dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

904

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

906

sclk_setting->Fcw_int = dividers.usSclk_fcw_int;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

907

sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

908

sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

909

sclk_setting->PllRange = dividers.ucSclkPllRange;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

911

sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

913

sclk_setting->SSc_En = dividers.ucSscEnable;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

914

sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

915

sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

916

sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1180

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1199

table->ACPILevel.SclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1206

table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1313

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1342

&dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1348

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1351

table->UvdLevel[count].DclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1357

(uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1373

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1400

table->VceLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1405

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1418

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1445

table->AcpLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

1449

table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

542

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

554

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

562

reference_divider = 1 + dividers.uc_pll_ref_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

565

fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

569

CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

571

CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

585

uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

611

sclk->SclkDid = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1199

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1231

table->VceLevel[count].Frequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1236

table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1312

struct pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1343

table->UvdLevel[count].VclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1347

table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1350

table->UvdLevel[count].DclkFrequency, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1354

table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

1930

pp_atomctrl_clock_dividers_vi dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2105

smu_data->bif_sclk_table[i], &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2112

PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

2115

PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

724

struct pp_atomctrl_clock_dividers_ai dividers;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

733

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

735

sclk_setting->Fcw_int = dividers.usSclk_fcw_int;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

736

sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

737

sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

738

sclk_setting->PllRange = dividers.ucSclkPllRange;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

740

sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

742

sclk_setting->SSc_En = dividers.ucSscEnable;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

743

sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

744

sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

745

sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1699

} dividers[] = {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1710

for (d = 0; d < ARRAY_SIZE(dividers); d++) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1712

for (i = 0; i < dividers[d].n_dividers; i++) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1713

unsigned int p = dividers[d].list[i];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2817

static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2827

for (d = 0; d < ARRAY_SIZE(dividers); d++) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2828

dco = afe_clock * dividers[d];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2835

best_div = dividers[d];

drivers/gpu/drm/radeon/btc_dpm.c

2526

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/btc_dpm.c

2576

0, false, &dividers);

drivers/gpu/drm/radeon/btc_dpm.c

2578

pi->ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/ci_dpm.c

2608

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ci_dpm.c

2625

table->UvdLevel[count].VclkFrequency, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

2629

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/ci_dpm.c

2633

table->UvdLevel[count].DclkFrequency, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

2637

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/ci_dpm.c

2651

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ci_dpm.c

2666

table->VceLevel[count].Frequency, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

2670

table->VceLevel[count].Divider = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/ci_dpm.c

2684

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ci_dpm.c

2699

table->AcpLevel[count].Frequency, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

2703

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/ci_dpm.c

2716

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ci_dpm.c

2731

table->SamuLevel[count].Frequency, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

2735

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/ci_dpm.c

2949

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ci_dpm.c

2970

table->ACPILevel.SclkFrequency, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

2974

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/ci_dpm.c

3120

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ci_dpm.c

3132

engine_clock, false, &dividers);

drivers/gpu/drm/radeon/ci_dpm.c

3136

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/radeon/ci_dpm.c

3137

fbdiv = dividers.fb_div & 0x3FFFFFF;

drivers/gpu/drm/radeon/ci_dpm.c

3145

u32 vco_freq = engine_clock * dividers.post_div;

drivers/gpu/drm/radeon/ci_dpm.c

3166

sclk->SclkDid = (u8)dividers.post_divider;

drivers/gpu/drm/radeon/cik.c

9429

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/cik.c

9433

clock, false, &dividers);

drivers/gpu/drm/radeon/cik.c

9439

tmp |= dividers.post_divider;

drivers/gpu/drm/radeon/cik.c

9468

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/cik.c

9472

ecclk, false, &dividers);

drivers/gpu/drm/radeon/cik.c

9486

tmp |= dividers.post_divider;

drivers/gpu/drm/radeon/cypress_dpm.c

2028

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/cypress_dpm.c

2059

0, false, &dividers);

drivers/gpu/drm/radeon/cypress_dpm.c

2061

pi->ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/cypress_dpm.c

493

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/cypress_dpm.c

500

memory_clock, strobe_mode, &dividers);

drivers/gpu/drm/radeon/cypress_dpm.c

508

dividers.post_div = 1;

drivers/gpu/drm/radeon/cypress_dpm.c

511

ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);

drivers/gpu/drm/radeon/cypress_dpm.c

518

mpll_ad_func_cntl |= CLKR(dividers.ref_div);

drivers/gpu/drm/radeon/cypress_dpm.c

519

mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);

drivers/gpu/drm/radeon/cypress_dpm.c

520

mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);

drivers/gpu/drm/radeon/cypress_dpm.c

521

mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);

drivers/gpu/drm/radeon/cypress_dpm.c

524

if (dividers.vco_mode)

drivers/gpu/drm/radeon/cypress_dpm.c

535

mpll_dq_func_cntl |= CLKR(dividers.ref_div);

drivers/gpu/drm/radeon/cypress_dpm.c

536

mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);

drivers/gpu/drm/radeon/cypress_dpm.c

537

mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);

drivers/gpu/drm/radeon/cypress_dpm.c

538

mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);

drivers/gpu/drm/radeon/cypress_dpm.c

546

if (dividers.vco_mode)

drivers/gpu/drm/radeon/cypress_dpm.c

554

u32 vco_freq = memory_clock * dividers.post_div;

drivers/gpu/drm/radeon/cypress_dpm.c

559

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

drivers/gpu/drm/radeon/cypress_dpm.c

566

(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);

drivers/gpu/drm/radeon/evergreen.c

1146

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/evergreen.c

1149

clock, false, &dividers);

drivers/gpu/drm/radeon/evergreen.c

1153

WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));

drivers/gpu/drm/radeon/kv_dpm.c

379

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/kv_dpm.c

383

sclk, false, &dividers);

drivers/gpu/drm/radeon/kv_dpm.c

387

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

drivers/gpu/drm/radeon/kv_dpm.c

664

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/kv_dpm.c

687

table->entries[i].vclk, false, &dividers);

drivers/gpu/drm/radeon/kv_dpm.c

690

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

drivers/gpu/drm/radeon/kv_dpm.c

693

table->entries[i].dclk, false, &dividers);

drivers/gpu/drm/radeon/kv_dpm.c

696

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

drivers/gpu/drm/radeon/kv_dpm.c

737

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/kv_dpm.c

755

table->entries[i].evclk, false, &dividers);

drivers/gpu/drm/radeon/kv_dpm.c

758

pi->vce_level[i].Divider = (u8)dividers.post_div;

drivers/gpu/drm/radeon/kv_dpm.c

798

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/kv_dpm.c

818

table->entries[i].clk, false, &dividers);

drivers/gpu/drm/radeon/kv_dpm.c

821

pi->samu_level[i].Divider = (u8)dividers.post_div;

drivers/gpu/drm/radeon/kv_dpm.c

864

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/kv_dpm.c

877

table->entries[i].clk, false, &dividers);

drivers/gpu/drm/radeon/kv_dpm.c

880

pi->acp_level[i].Divider = (u8)dividers.post_div;

drivers/gpu/drm/radeon/ni.c

2694

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ni.c

2698

ecclk, false, &dividers);

drivers/gpu/drm/radeon/ni.c

2710

WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));

drivers/gpu/drm/radeon/ni_dpm.c

2004

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ni_dpm.c

2018

engine_clock, false, &dividers);

drivers/gpu/drm/radeon/ni_dpm.c

2022

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/radeon/ni_dpm.c

2025

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;

drivers/gpu/drm/radeon/ni_dpm.c

2030

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

drivers/gpu/drm/radeon/ni_dpm.c

2031

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

drivers/gpu/drm/radeon/ni_dpm.c

2042

u32 vco_freq = engine_clock * dividers.post_div;

drivers/gpu/drm/radeon/ni_dpm.c

2177

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ni_dpm.c

2184

memory_clock, strobe_mode, &dividers);

drivers/gpu/drm/radeon/ni_dpm.c

2192

dividers.post_div = 1;

drivers/gpu/drm/radeon/ni_dpm.c

2195

ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);

drivers/gpu/drm/radeon/ni_dpm.c

2202

mpll_ad_func_cntl |= CLKR(dividers.ref_div);

drivers/gpu/drm/radeon/ni_dpm.c

2203

mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);

drivers/gpu/drm/radeon/ni_dpm.c

2204

mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);

drivers/gpu/drm/radeon/ni_dpm.c

2205

mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);

drivers/gpu/drm/radeon/ni_dpm.c

2208

if (dividers.vco_mode)

drivers/gpu/drm/radeon/ni_dpm.c

2219

mpll_dq_func_cntl |= CLKR(dividers.ref_div);

drivers/gpu/drm/radeon/ni_dpm.c

2220

mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);

drivers/gpu/drm/radeon/ni_dpm.c

2221

mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);

drivers/gpu/drm/radeon/ni_dpm.c

2222

mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);

drivers/gpu/drm/radeon/ni_dpm.c

2230

if (dividers.vco_mode)

drivers/gpu/drm/radeon/ni_dpm.c

2238

u32 vco_freq = memory_clock * dividers.post_div;

drivers/gpu/drm/radeon/ni_dpm.c

2243

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

drivers/gpu/drm/radeon/ni_dpm.c

2250

(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);

drivers/gpu/drm/radeon/ni_dpm.c

4050

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/ni_dpm.c

4103

0, false, &dividers);

drivers/gpu/drm/radeon/ni_dpm.c

4105

pi->ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/radeon.h

298

struct atom_clock_dividers *dividers);

drivers/gpu/drm/radeon/radeon_atombios.c

2829

struct atom_clock_dividers *dividers)

drivers/gpu/drm/radeon/radeon_atombios.c

2836

memset(dividers, 0, sizeof(struct atom_clock_dividers));

drivers/gpu/drm/radeon/radeon_atombios.c

2849

dividers->post_div = args.v1.ucPostDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2850

dividers->fb_div = args.v1.ucFbDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2851

dividers->enable_post_div = true;

drivers/gpu/drm/radeon/radeon_atombios.c

2863

dividers->post_div = args.v2.ucPostDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2864

dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);

drivers/gpu/drm/radeon/radeon_atombios.c

2865

dividers->ref_div = args.v2.ucAction;

drivers/gpu/drm/radeon/radeon_atombios.c

2867

dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?

drivers/gpu/drm/radeon/radeon_atombios.c

2869

dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;

drivers/gpu/drm/radeon/radeon_atombios.c

2871

dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;

drivers/gpu/drm/radeon/radeon_atombios.c

2878

dividers->post_div = args.v3.ucPostDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2879

dividers->enable_post_div = (args.v3.ucCntlFlag &

drivers/gpu/drm/radeon/radeon_atombios.c

2881

dividers->enable_dithen = (args.v3.ucCntlFlag &

drivers/gpu/drm/radeon/radeon_atombios.c

2883

dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

drivers/gpu/drm/radeon/radeon_atombios.c

2884

dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);

drivers/gpu/drm/radeon/radeon_atombios.c

2885

dividers->ref_div = args.v3.ucRefDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2886

dividers->vco_mode = (args.v3.ucCntlFlag &

drivers/gpu/drm/radeon/radeon_atombios.c

2898

dividers->post_div = args.v5.ucPostDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2899

dividers->enable_post_div = (args.v5.ucCntlFlag &

drivers/gpu/drm/radeon/radeon_atombios.c

2901

dividers->enable_dithen = (args.v5.ucCntlFlag &

drivers/gpu/drm/radeon/radeon_atombios.c

2903

dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);

drivers/gpu/drm/radeon/radeon_atombios.c

2904

dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);

drivers/gpu/drm/radeon/radeon_atombios.c

2905

dividers->ref_div = args.v5.ucRefDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2906

dividers->vco_mode = (args.v5.ucCntlFlag &

drivers/gpu/drm/radeon/radeon_atombios.c

2917

dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2918

dividers->real_clock = le32_to_cpu(args.v4.ulClock);

drivers/gpu/drm/radeon/radeon_atombios.c

2928

dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);

drivers/gpu/drm/radeon/radeon_atombios.c

2929

dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);

drivers/gpu/drm/radeon/radeon_atombios.c

2930

dividers->ref_div = args.v6_out.ucPllRefDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2931

dividers->post_div = args.v6_out.ucPllPostDiv;

drivers/gpu/drm/radeon/radeon_atombios.c

2932

dividers->flags = args.v6_out.ucPllCntlFlag;

drivers/gpu/drm/radeon/radeon_atombios.c

2933

dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);

drivers/gpu/drm/radeon/radeon_atombios.c

2934

dividers->post_divider = args.v6_out.ulClock.ucPostDiv;

drivers/gpu/drm/radeon/rs780_dpm.c

1032

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rs780_dpm.c

1043

ps->sclk_high, false, &dividers);

drivers/gpu/drm/radeon/rs780_dpm.c

1047

rs780_force_fbdiv(rdev, dividers.fb_div);

drivers/gpu/drm/radeon/rs780_dpm.c

1050

ps->sclk_low, false, &dividers);

drivers/gpu/drm/radeon/rs780_dpm.c

1054

rs780_force_fbdiv(rdev, dividers.fb_div);

drivers/gpu/drm/radeon/rs780_dpm.c

78

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rs780_dpm.c

83

default_state->sclk_low, false, &dividers);

drivers/gpu/drm/radeon/rs780_dpm.c

87

r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);

drivers/gpu/drm/radeon/rs780_dpm.c

88

r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);

drivers/gpu/drm/radeon/rs780_dpm.c

89

r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);

drivers/gpu/drm/radeon/rs780_dpm.c

91

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv6xx_dpm.c

142

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv6xx_dpm.c

145

clock, false, &dividers);

drivers/gpu/drm/radeon/rv6xx_dpm.c

149

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv6xx_dpm.c

150

step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1934

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv6xx_dpm.c

1957

0, false, &dividers);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1959

pi->spll_ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/rv6xx_dpm.c

1964

0, false, &dividers);

drivers/gpu/drm/radeon/rv6xx_dpm.c

1966

pi->mpll_ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/rv6xx_dpm.c

526

struct atom_clock_dividers *dividers,

drivers/gpu/drm/radeon/rv6xx_dpm.c

529

return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /

drivers/gpu/drm/radeon/rv6xx_dpm.c

530

(dividers->ref_div + 1);

drivers/gpu/drm/radeon/rv6xx_dpm.c

553

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv6xx_dpm.c

560

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {

drivers/gpu/drm/radeon/rv6xx_dpm.c

561

vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,

drivers/gpu/drm/radeon/rv6xx_dpm.c

567

(ref_clk / (dividers.ref_div + 1)),

drivers/gpu/drm/radeon/rv6xx_dpm.c

573

(ref_clk / (dividers.ref_div + 1)));

drivers/gpu/drm/radeon/rv6xx_dpm.c

600

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv6xx_dpm.c

602

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))

drivers/gpu/drm/radeon/rv6xx_dpm.c

606

rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);

drivers/gpu/drm/radeon/rv6xx_dpm.c

607

rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);

drivers/gpu/drm/radeon/rv6xx_dpm.c

608

rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);

drivers/gpu/drm/radeon/rv6xx_dpm.c

610

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv6xx_dpm.c

633

struct atom_clock_dividers *dividers,

drivers/gpu/drm/radeon/rv6xx_dpm.c

646

*dividers = req_dividers;

drivers/gpu/drm/radeon/rv6xx_dpm.c

656

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv6xx_dpm.c

666

&dividers,

drivers/gpu/drm/radeon/rv6xx_dpm.c

672

&dividers,

drivers/gpu/drm/radeon/rv6xx_dpm.c

678

&dividers,

drivers/gpu/drm/radeon/rv6xx_dpm.c

685

(ref_clk / (dividers.ref_div + 1)),

drivers/gpu/drm/radeon/rv6xx_dpm.c

691

(ref_clk / (dividers.ref_div + 1)));

drivers/gpu/drm/radeon/rv730_dpm.c

128

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv730_dpm.c

133

memory_clock, false, &dividers);

drivers/gpu/drm/radeon/rv730_dpm.c

137

reference_divider = dividers.ref_div + 1;

drivers/gpu/drm/radeon/rv730_dpm.c

139

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv730_dpm.c

140

post_divider = ((dividers.post_div >> 4) & 0xf) +

drivers/gpu/drm/radeon/rv730_dpm.c

141

(dividers.post_div & 0xf) + 2;

drivers/gpu/drm/radeon/rv730_dpm.c

146

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv730_dpm.c

152

mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);

drivers/gpu/drm/radeon/rv730_dpm.c

153

mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);

drivers/gpu/drm/radeon/rv730_dpm.c

154

mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);

drivers/gpu/drm/radeon/rv730_dpm.c

157

mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);

drivers/gpu/drm/radeon/rv730_dpm.c

158

if (dividers.enable_dithen)

drivers/gpu/drm/radeon/rv730_dpm.c

171

u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);

drivers/gpu/drm/radeon/rv730_dpm.c

42

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv730_dpm.c

55

engine_clock, false, &dividers);

drivers/gpu/drm/radeon/rv730_dpm.c

59

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/radeon/rv730_dpm.c

61

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv730_dpm.c

62

post_divider = ((dividers.post_div >> 4) & 0xf) +

drivers/gpu/drm/radeon/rv730_dpm.c

63

(dividers.post_div & 0xf) + 2;

drivers/gpu/drm/radeon/rv730_dpm.c

72

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv730_dpm.c

77

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

drivers/gpu/drm/radeon/rv730_dpm.c

78

spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);

drivers/gpu/drm/radeon/rv730_dpm.c

79

spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);

drivers/gpu/drm/radeon/rv740_dpm.c

123

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv740_dpm.c

136

engine_clock, false, &dividers);

drivers/gpu/drm/radeon/rv740_dpm.c

140

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/radeon/rv740_dpm.c

142

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

drivers/gpu/drm/radeon/rv740_dpm.c

147

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

drivers/gpu/drm/radeon/rv740_dpm.c

148

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

drivers/gpu/drm/radeon/rv740_dpm.c

159

u32 vco_freq = engine_clock * dividers.post_div;

drivers/gpu/drm/radeon/rv740_dpm.c

198

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv740_dpm.c

204

memory_clock, false, &dividers);

drivers/gpu/drm/radeon/rv740_dpm.c

208

ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div);

drivers/gpu/drm/radeon/rv740_dpm.c

215

mpll_ad_func_cntl |= CLKR(dividers.ref_div);

drivers/gpu/drm/radeon/rv740_dpm.c

216

mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);

drivers/gpu/drm/radeon/rv740_dpm.c

217

mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);

drivers/gpu/drm/radeon/rv740_dpm.c

218

mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);

drivers/gpu/drm/radeon/rv740_dpm.c

221

if (dividers.vco_mode)

drivers/gpu/drm/radeon/rv740_dpm.c

232

mpll_dq_func_cntl |= CLKR(dividers.ref_div);

drivers/gpu/drm/radeon/rv740_dpm.c

233

mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);

drivers/gpu/drm/radeon/rv740_dpm.c

234

mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);

drivers/gpu/drm/radeon/rv740_dpm.c

235

mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);

drivers/gpu/drm/radeon/rv740_dpm.c

238

if (dividers.vco_mode)

drivers/gpu/drm/radeon/rv740_dpm.c

246

u32 vco_freq = memory_clock * dividers.post_div;

drivers/gpu/drm/radeon/rv740_dpm.c

251

u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);

drivers/gpu/drm/radeon/rv740_dpm.c

258

(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);

drivers/gpu/drm/radeon/rv770_dpm.c

2347

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv770_dpm.c

2375

0, false, &dividers);

drivers/gpu/drm/radeon/rv770_dpm.c

2377

pi->ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/rv770_dpm.c

322

struct atom_clock_dividers *dividers,

drivers/gpu/drm/radeon/rv770_dpm.c

334

post_divider = dividers->post_div;

drivers/gpu/drm/radeon/rv770_dpm.c

335

reference_divider = dividers->ref_div;

drivers/gpu/drm/radeon/rv770_dpm.c

404

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv770_dpm.c

412

memory_clock, false, &dividers);

drivers/gpu/drm/radeon/rv770_dpm.c

416

if ((dividers.ref_div < 1) || (dividers.ref_div > 5))

drivers/gpu/drm/radeon/rv770_dpm.c

421

&dividers, &clkf, &clkfrac);

drivers/gpu/drm/radeon/rv770_dpm.c

423

ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);

drivers/gpu/drm/radeon/rv770_dpm.c

434

mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);

drivers/gpu/drm/radeon/rv770_dpm.c

440

if (dividers.vco_mode)

drivers/gpu/drm/radeon/rv770_dpm.c

449

&dividers, &clkf, &clkfrac);

drivers/gpu/drm/radeon/rv770_dpm.c

453

ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk);

drivers/gpu/drm/radeon/rv770_dpm.c

462

mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]);

drivers/gpu/drm/radeon/rv770_dpm.c

468

if (dividers.vco_mode)

drivers/gpu/drm/radeon/rv770_dpm.c

490

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/rv770_dpm.c

508

engine_clock, false, &dividers);

drivers/gpu/drm/radeon/rv770_dpm.c

512

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/radeon/rv770_dpm.c

514

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv770_dpm.c

515

post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2;

drivers/gpu/drm/radeon/rv770_dpm.c

523

if (dividers.enable_post_div)

drivers/gpu/drm/radeon/rv770_dpm.c

528

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

drivers/gpu/drm/radeon/rv770_dpm.c

529

spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);

drivers/gpu/drm/radeon/rv770_dpm.c

530

spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);

drivers/gpu/drm/radeon/si_dpm.c

4732

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/si_dpm.c

4746

engine_clock, false, &dividers);

drivers/gpu/drm/radeon/si_dpm.c

4750

reference_divider = 1 + dividers.ref_div;

drivers/gpu/drm/radeon/si_dpm.c

4752

tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;

drivers/gpu/drm/radeon/si_dpm.c

4757

spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);

drivers/gpu/drm/radeon/si_dpm.c

4758

spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);

drivers/gpu/drm/radeon/si_dpm.c

4769

u32 vco_freq = engine_clock * dividers.post_div;

drivers/gpu/drm/radeon/si_dpm.c

6848

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/si_dpm.c

6924

0, false, &dividers);

drivers/gpu/drm/radeon/si_dpm.c

6926

pi->ref_div = dividers.ref_div + 1;

drivers/gpu/drm/radeon/sumo_dpm.c

549

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/sumo_dpm.c

553

pl->sclk, false, &dividers);

drivers/gpu/drm/radeon/sumo_dpm.c

557

sumo_set_divider_value(rdev, index, dividers.post_div);

drivers/gpu/drm/radeon/sumo_dpm.c

784

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/sumo_dpm.c

789

false, &dividers);

drivers/gpu/drm/radeon/sumo_dpm.c

793

WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);

drivers/gpu/drm/radeon/trinity_dpm.c

319

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/trinity_dpm.c

326

25000, false, &dividers);

drivers/gpu/drm/radeon/trinity_dpm.c

334

value |= PDS_DIV(dividers.post_div);

drivers/gpu/drm/radeon/trinity_dpm.c

538

struct atom_clock_dividers dividers;

drivers/gpu/drm/radeon/trinity_dpm.c

544

sclk, false, &dividers);

drivers/gpu/drm/radeon/trinity_dpm.c

550

value |= CLK_DIVIDER(dividers.post_div);

drivers/gpu/drm/radeon/trinity_dpm.c

554

sclk/2, false, &dividers);

drivers/gpu/drm/radeon/trinity_dpm.c

560

value |= PD_SCLK_DIVIDER(dividers.post_div);

sound/soc/sunxi/sun4i-i2s.c

294

const struct sun4i_i2s_clk_div *dividers = i2s->variant->bclk_dividers;

sound/soc/sunxi/sun4i-i2s.c

299

const struct sun4i_i2s_clk_div *bdiv = &dividers[i];

sound/soc/sunxi/sun4i-i2s.c

312

const struct sun4i_i2s_clk_div *dividers = i2s->variant->mclk_dividers;

sound/soc/sunxi/sun4i-i2s.c

317

const struct sun4i_i2s_clk_div *mdiv = &dividers[i];