divide
.set dz_bit,2 | divide by zero
.set adz_bit,4 | accrued divide by zero
.set adz_mask,0x00000010 | accrued divide by zero
u32 divide, u32 divisor,
t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor);
divide(freq / 333, sysclock, NULL, &frequency_shift);
div = divide(p->frequency * 3, 500000) + 217;
permille_failed = divide(failed_packets * 1000, nr_packets);
average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
(unsigned long long)divide(permille_failed, 10),
(unsigned long long)divide(average_tries, 100),
usbn_clk_ctl.s.divide = divisor;
__BITFIELD_FIELD(u64 divide : 3,
int divide;
divide = 1;
while ((prescale > 5) && (divide < 32)) {
divide <<= 1;
divide >>= 1;
for (; divide < 31; divide++)
((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
if (divide == 0) {
divide++;
} else if (divide > 1)
divide--;
__maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */