Symbol: div_mask
drivers/clk/actions/owl-factor.c
159
val &= div_mask(factor_hw);
drivers/clk/actions/owl-factor.c
194
if (val > div_mask(factor_hw))
drivers/clk/actions/owl-factor.c
195
val = div_mask(factor_hw);
drivers/clk/actions/owl-factor.c
199
reg &= ~(div_mask(factor_hw) << factor_hw->shift);
drivers/clk/at91/at91sam9n12.c
76
.div_mask = GENMASK(17, 16),
drivers/clk/at91/at91sam9x5.c
63
.div_mask = GENMASK(17, 16),
drivers/clk/at91/clk-peripheral.c
177
periph->layout->div_mask | periph->layout->cmd |
drivers/clk/at91/clk-peripheral.c
179
field_prep(periph->layout->div_mask, periph->div) |
drivers/clk/at91/clk-peripheral.c
246
periph->div = field_get(periph->layout->div_mask, status);
drivers/clk/at91/clk-peripheral.c
498
if (layout->div_mask)
drivers/clk/at91/clk-sam9x60-pll.c
354
core->layout->div_mask | ena_msk,
drivers/clk/at91/clk-sam9x60-pll.c
376
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
drivers/clk/at91/clk-sam9x60-pll.c
469
for (divid = 1; divid < core->layout->div_mask; divid++) {
drivers/clk/at91/clk-sam9x60-pll.c
531
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
drivers/clk/at91/clk-sam9x60-pll.c
587
cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
drivers/clk/at91/dt-compat.c
113
.div_mask = GENMASK(17, 16),
drivers/clk/at91/pmc.h
101
u32 div_mask;
drivers/clk/at91/pmc.h
61
u32 div_mask;
drivers/clk/at91/sam9x60.c
63
.div_mask = GENMASK(7, 0),
drivers/clk/at91/sam9x7.c
165
.div_mask = GENMASK(7, 0),
drivers/clk/at91/sam9x7.c
173
.div_mask = GENMASK(7, 0),
drivers/clk/at91/sam9x7.c
182
.div_mask = GENMASK(19, 12),
drivers/clk/at91/sama5d3.c
37
.div_mask = GENMASK(17, 16),
drivers/clk/at91/sama7d65.c
82
.div_mask = GENMASK(7, 0),
drivers/clk/at91/sama7d65.c
90
.div_mask = GENMASK(19, 12),
drivers/clk/at91/sama7g5.c
77
.div_mask = GENMASK(7, 0),
drivers/clk/at91/sama7g5.c
85
.div_mask = GENMASK(19, 12),
drivers/clk/clk-vt8500.c
118
u32 div = readl(cdev->div_reg) & cdev->div_mask;
drivers/clk/clk-vt8500.c
121
if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
drivers/clk/clk-vt8500.c
126
div = (cdev->div_mask + 1);
drivers/clk/clk-vt8500.c
150
if ((cdev->div_mask == 0x3F) && (divisor > 31))
drivers/clk/clk-vt8500.c
170
if (divisor == cdev->div_mask + 1)
drivers/clk/clk-vt8500.c
174
if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
drivers/clk/clk-vt8500.c
182
if (divisor > cdev->div_mask) {
drivers/clk/clk-vt8500.c
23
unsigned int div_mask;
drivers/clk/clk-vt8500.c
263
dev_clk->div_mask = 0x1f;
drivers/clk/clk-vt8500.c
265
of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
drivers/clk/hisilicon/clkdivider-hi6220.c
117
max_div = div_mask(width) + 1;
drivers/clk/hisilicon/clkdivider-hi6220.c
52
val &= div_mask(dclk->width);
drivers/clk/hisilicon/clkdivider-hi6220.c
82
data &= ~(div_mask(dclk->width) << dclk->shift);
drivers/clk/imx/clk-fixup-div.c
66
if (value > div_mask(div))
drivers/clk/imx/clk-fixup-div.c
67
value = div_mask(div);
drivers/clk/imx/clk-fixup-div.c
72
val &= ~(div_mask(div) << div->shift);
drivers/clk/imx/clk-pllv3.c
115
u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
drivers/clk/imx/clk-pllv3.c
144
val &= ~(pll->div_mask << pll->div_shift);
drivers/clk/imx/clk-pllv3.c
164
u32 div = readl_relaxed(pll->base) & pll->div_mask;
drivers/clk/imx/clk-pllv3.c
201
val &= ~pll->div_mask;
drivers/clk/imx/clk-pllv3.c
223
u32 div = readl_relaxed(pll->base) & pll->div_mask;
drivers/clk/imx/clk-pllv3.c
290
val &= ~pll->div_mask;
drivers/clk/imx/clk-pllv3.c
358
mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
drivers/clk/imx/clk-pllv3.c
384
val &= ~pll->div_mask; /* clear bit for mfi=20 */
drivers/clk/imx/clk-pllv3.c
386
val |= pll->div_mask; /* set bit for mfi=22 */
drivers/clk/imx/clk-pllv3.c
421
u32 div_mask)
drivers/clk/imx/clk-pllv3.c
479
pll->div_mask = div_mask;
drivers/clk/imx/clk-pllv3.c
52
u32 div_mask;
drivers/clk/imx/clk.h
112
#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
drivers/clk/imx/clk.h
113
to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
drivers/clk/imx/clk.h
261
const char *parent_name, void __iomem *base, u32 div_mask);
drivers/clk/mmp/clk-mix.c
26
unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
drivers/clk/mmp/clk-mix.c
31
return div_mask;
drivers/clk/mmp/clk-mix.c
33
return 1 << div_mask;
drivers/clk/mmp/clk-mix.c
40
return div_mask + 1;
drivers/clk/nxp/clk-lpc32xx.c
1479
static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
drivers/clk/nxp/clk-lpc32xx.c
1485
if (!(val & div_mask)) {
drivers/clk/nxp/clk-lpc32xx.c
1487
val |= BIT(__ffs(div_mask));
drivers/clk/nxp/clk-lpc32xx.c
1490
regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
drivers/clk/nxp/clk-lpc32xx.c
954
val &= div_mask(divider->width);
drivers/clk/nxp/clk-lpc32xx.c
970
bestdiv &= div_mask(divider->width);
drivers/clk/nxp/clk-lpc32xx.c
992
div_mask(divider->width) << divider->shift,
drivers/clk/rockchip/clk-half-divider.c
120
value = min_t(unsigned int, value, div_mask(divider->width));
drivers/clk/rockchip/clk-half-divider.c
128
val = div_mask(divider->width) << (divider->shift + 16);
drivers/clk/rockchip/clk-half-divider.c
131
val &= ~(div_mask(divider->width) << divider->shift);
drivers/clk/rockchip/clk-half-divider.c
29
val &= div_mask(divider->width);
drivers/clk/rockchip/clk-half-divider.c
46
maxdiv = div_mask(width);
drivers/clk/rockchip/clk-half-divider.c
88
bestdiv = div_mask(width);
drivers/clk/samsung/clk-cpu.c
281
unsigned long div = 0, div_mask = DIV_MASK;
drivers/clk/samsung/clk-cpu.c
303
div_mask |= E4210_DIV0_ATB_MASK;
drivers/clk/samsung/clk-cpu.c
306
exynos_set_safe_div(cpuclk, div, div_mask);
drivers/clk/samsung/clk-cpu.c
390
unsigned long div = 0, div_mask = DIV_MASK;
drivers/clk/samsung/clk-cpu.c
401
exynos_set_safe_div(cpuclk, div, div_mask);
drivers/clk/tegra/clk-divider.c
104
val &= ~(div_mask(divider) << divider->shift);
drivers/clk/tegra/clk-divider.c
17
#define get_max_div(d) div_mask(d)
drivers/clk/tegra/clk-divider.c
49
div = (reg >> divider->shift) & div_mask(divider);
drivers/clk/tegra/clk-utils.c
39
if (divider_ux1 > div_mask(width))
drivers/clk/tegra/clk-utils.c
40
return div_mask(width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
229
val &= div_mask(divider->width);
drivers/clk/xilinx/clk-xlnx-clock-wizard.c
733
div = val & div_mask(divider->width);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
617
val &= div_mask(width);
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
656
val &= ~(div_mask(width) << shift);
drivers/i2c/busses/i2c-brcmstb.c
115
.div_mask = 0
drivers/i2c/busses/i2c-brcmstb.c
120
.div_mask = 0
drivers/i2c/busses/i2c-brcmstb.c
125
.div_mask = 0
drivers/i2c/busses/i2c-brcmstb.c
130
.div_mask = 0
drivers/i2c/busses/i2c-brcmstb.c
135
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
drivers/i2c/busses/i2c-brcmstb.c
140
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
drivers/i2c/busses/i2c-brcmstb.c
145
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
drivers/i2c/busses/i2c-brcmstb.c
150
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
drivers/i2c/busses/i2c-brcmstb.c
561
bsc_clk[i].div_mask);
drivers/i2c/busses/i2c-brcmstb.c
83
u32 div_mask;
drivers/mfd/db8500-prcmu.c
1534
div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
drivers/mfd/db8500-prcmu.c
1898
val &= ~dsiescclk[n].div_mask;
drivers/mfd/db8500-prcmu.c
522
u32 div_mask;
drivers/mfd/db8500-prcmu.c
529
.div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
drivers/mfd/db8500-prcmu.c
534
.div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
drivers/mfd/db8500-prcmu.c
539
.div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
drivers/mfd/db8500-prcmu.c
645
u32 div_mask;
drivers/mfd/db8500-prcmu.c
655
div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
drivers/mfd/db8500-prcmu.c
660
div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
drivers/mfd/db8500-prcmu.c
671
if (val & div_mask) {
drivers/mfd/db8500-prcmu.c
678
if ((val & mask & ~div_mask) != bits) {
drivers/sh/clk/cpg.c
126
idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
drivers/sh/clk/cpg.c
142
value &= ~(clk->div_mask << clk->enable_bit);
drivers/sh/clk/cpg.c
155
if (clk->div_mask == SH_CLK_DIV6_MSK) {
drivers/sh/clk/cpg.c
178
val |= clk->div_mask;
include/linux/sh_clk.h
157
.div_mask = SH_CLK_DIV4_MSK, \
include/linux/sh_clk.h
181
.div_mask = SH_CLK_DIV6_MSK, \
include/linux/sh_clk.h
193
.div_mask = SH_CLK_DIV6_MSK, \
include/linux/sh_clk.h
60
unsigned int div_mask;
sound/soc/fsl/fsl_mqs.c
126
mqs_priv->soc->div_mask,
sound/soc/fsl/fsl_mqs.c
359
.div_mask = MQS_CLK_DIV_MASK,
sound/soc/fsl/fsl_mqs.c
372
.div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
sound/soc/fsl/fsl_mqs.c
385
.div_mask = GENMASK(15, 8),
sound/soc/fsl/fsl_mqs.c
399
.div_mask = GENMASK(15, 8),
sound/soc/fsl/fsl_mqs.c
412
.div_mask = GENMASK(16, 9),
sound/soc/fsl/fsl_mqs.c
426
.div_mask = GENMASK(15, 8),
sound/soc/fsl/fsl_mqs.c
440
.div_mask = GENMASK(15, 8),
sound/soc/fsl/fsl_mqs.c
63
int div_mask;
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
412
int div_mask;
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
427
.div_mask = APLL12_CK_DIV0_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
440
.div_mask = APLL12_CK_DIV1_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
453
.div_mask = APLL12_CK_DIV2_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
466
.div_mask = APLL12_CK_DIV3_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
479
.div_mask = APLL12_CK_DIV4_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
492
.div_mask = APLL12_CK_DIVB_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
502
.div_mask = APLL12_CK_DIV5_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
515
.div_mask = APLL12_CK_DIV6_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
528
.div_mask = APLL12_CK_DIV7_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
541
.div_mask = APLL12_CK_DIV8_MASK,
sound/soc/mediatek/mt8192/mt8192-afe-clk.c
554
.div_mask = APLL12_CK_DIV9_MASK,