div_factor
unsigned int div, div_factor;
div_factor = div_to_div_factor(div);
div = div_factor_to_div(div_factor);
unsigned int div_factor;
regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
return parent_rate / div_factor_to_div(div_factor);
unsigned int div_factor = div_to_div_factor(parent_rate / rate);
DIV_CTL1_DIV_FACTOR_MASK, div_factor);
div_factor);
static inline unsigned int div_factor_to_div(unsigned int div_factor)
if (!div_factor)
div_factor = 1;
return 1 << (div_factor - 1);
unsigned int div_factor)
unsigned int div = div_factor_to_div(div_factor);
unsigned int div_factor;
regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
s64 conn_period, div_factor;
div_factor = div64_s64(ref_phase, conn_period);
ref_phase -= conn_period * div_factor;
dto_params.refclk_hz *= e->div_factor;
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
unsigned short div_factor;
u32 div_factor = 1, mul_factor, fr = 0;
while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK)
div_factor++;
if (div_factor > 31)
div_factor = 31;
mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor;
return (fr << 14) | (div_factor << 8) | mul_factor;
u32 div_factor, N , A, x;
div_factor = (frequency * ref) / 40; /* local osc = 4Mhz */
x = div_factor / psc;
u32 div_factor = 2;
div_factor = 4;
div_factor = 1;
frame_size = base_res_mbs * (16 * 16) * 3 / 2 / div_factor;
u32 div_factor = 1;
div_factor = 4;
div_factor = 1;
div_factor = 2;
frame_size = base_res_mbs * MB_SIZE_IN_PIXEL * 3 / 2 / div_factor;
#define _write_cp_info(name_str, name, offset, start, width, div_factor)\
val |= (name / div_factor) << start;\
#define _write_pp_info(name_str, name, offset, start, width, div_factor)\
val |= (name / div_factor) << start;\
KUNIT_EXPECT_EQ(test, entry_val + div_factor, exit_val);
KUNIT_EXPECT_EQ(test, entry_val + div_factor, exit_val);
KUNIT_EXPECT_EQ(test, entry_val + div_factor, exit_val);
KUNIT_EXPECT_EQ(test, entry_val + div_factor, exit_val);
entry_only_val = (rand1 / div_factor);
entry_val = (rand1 / div_factor);
KUNIT_EXPECT_EQ(current_test, ret, (rand1 / div_factor));
KUNIT_EXPECT_EQ(test, (rand1 / div_factor), entry_only_val);
KUNIT_EXPECT_EQ(test, (rand1 / div_factor), entry_val);
KUNIT_EXPECT_EQ(test, (rand1 / div_factor), exit_val);
return (value / div_factor);
rand1 = get_random_u32_above(div_factor);
return (value / div_factor) + 1;
entry_val = (rand1 / div_factor);
KUNIT_EXPECT_EQ(current_test, ret, (rand1 / div_factor) + 1);
KUNIT_EXPECT_EQ(current_test, ret, (rand1 / div_factor));
KUNIT_EXPECT_EQ(current_test, entry_val, (rand1 / div_factor));
exit_val = entry_val + div_factor;
preh_val = (rand1 / div_factor) + 1;
KUNIT_EXPECT_EQ(current_test, preh_val, (rand1 / div_factor) + 1);
posth_val = preh_val + div_factor;
krph_val = (rand1 / div_factor);
KUNIT_EXPECT_EQ(current_test, ret, rand1 / div_factor);
KUNIT_EXPECT_EQ(current_test, ret, (rand1 / div_factor) + 1);
return (value / div_factor);
return (value / div_factor);
rand1 = get_random_u32_above(div_factor);
posth_val = preh_val + div_factor;
return (value / div_factor) + 1;
u32 div_factor;
div_factor = mclk_rate / dmic_sample_rate;
switch (div_factor) {
u32 div_factor;
div_factor = mclk_rate / dmic_clk_rate;
switch (div_factor) {
__func__, div_factor, mclk_rate, dmic_clk_rate);