Symbol: div_data
drivers/clk/clk-npcm7xx.c
486
const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
drivers/clk/clk-npcm7xx.c
488
hw = clk_hw_register_divider(NULL, div_data->name,
drivers/clk/clk-npcm7xx.c
489
div_data->parent_name,
drivers/clk/clk-npcm7xx.c
490
div_data->flags,
drivers/clk/clk-npcm7xx.c
491
clk_base + div_data->reg,
drivers/clk/clk-npcm7xx.c
492
div_data->shift, div_data->width,
drivers/clk/clk-npcm7xx.c
493
div_data->clk_divider_flags, &npcm7xx_clk_lock);
drivers/clk/clk-npcm7xx.c
499
if (div_data->onecell_idx >= 0)
drivers/clk/clk-npcm7xx.c
500
npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
drivers/clk/clk-npcm8xx.c
372
struct npcm8xx_clk_div_data *div_data = &npcm8xx_pre_divs[i];
drivers/clk/clk-npcm8xx.c
374
hw = devm_clk_hw_register_divider_parent_hw(dev, div_data->name,
drivers/clk/clk-npcm8xx.c
375
div_data->parent_hw,
drivers/clk/clk-npcm8xx.c
376
div_data->flags,
drivers/clk/clk-npcm8xx.c
377
clk_base + div_data->reg,
drivers/clk/clk-npcm8xx.c
378
div_data->shift,
drivers/clk/clk-npcm8xx.c
379
div_data->width,
drivers/clk/clk-npcm8xx.c
380
div_data->clk_divider_flags,
drivers/clk/clk-npcm8xx.c
384
div_data->hw = *hw;
drivers/clk/clk-npcm8xx.c
386
if (div_data->onecell_idx >= 0)
drivers/clk/clk-npcm8xx.c
387
npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
drivers/clk/clk-npcm8xx.c
392
struct npcm8xx_clk_div_data *div_data = &npcm8xx_divs[i];
drivers/clk/clk-npcm8xx.c
394
hw = devm_clk_hw_register_divider_parent_hw(dev, div_data->name,
drivers/clk/clk-npcm8xx.c
395
div_data->parent_hw,
drivers/clk/clk-npcm8xx.c
396
div_data->flags,
drivers/clk/clk-npcm8xx.c
397
clk_base + div_data->reg,
drivers/clk/clk-npcm8xx.c
398
div_data->shift,
drivers/clk/clk-npcm8xx.c
399
div_data->width,
drivers/clk/clk-npcm8xx.c
400
div_data->clk_divider_flags,
drivers/clk/clk-npcm8xx.c
405
if (div_data->onecell_idx >= 0)
drivers/clk/clk-npcm8xx.c
406
npcm8xx_clk_data->hws[div_data->onecell_idx] = hw;
drivers/clk/clk-stm32f4.c
605
static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
drivers/clk/clk-stm32f4.c
977
div_data[i].shift,
drivers/clk/clk-stm32f4.c
978
div_data[i].width,
drivers/clk/clk-stm32f4.c
979
div_data[i].flag_div,
drivers/clk/clk-stm32f4.c
980
div_data[i].div_table,
drivers/clk/clk-versaclock3.c
497
const struct vc3_div_data *div_data = vc3->data;
drivers/clk/clk-versaclock3.c
500
regmap_read(vc3->regmap, div_data->offs, &val);
drivers/clk/clk-versaclock3.c
501
val >>= div_data->shift;
drivers/clk/clk-versaclock3.c
502
val &= VC3_DIV_MASK(div_data->width);
drivers/clk/clk-versaclock3.c
504
return divider_recalc_rate(hw, parent_rate, val, div_data->table,
drivers/clk/clk-versaclock3.c
505
div_data->flags, div_data->width);
drivers/clk/clk-versaclock3.c
512
const struct vc3_div_data *div_data = vc3->data;
drivers/clk/clk-versaclock3.c
516
if (div_data->flags & CLK_DIVIDER_READ_ONLY) {
drivers/clk/clk-versaclock3.c
517
regmap_read(vc3->regmap, div_data->offs, &bestdiv);
drivers/clk/clk-versaclock3.c
518
bestdiv >>= div_data->shift;
drivers/clk/clk-versaclock3.c
519
bestdiv &= VC3_DIV_MASK(div_data->width);
drivers/clk/clk-versaclock3.c
520
bestdiv = vc3_get_div(div_data->table, bestdiv, div_data->flags);
drivers/clk/clk-versaclock3.c
526
return divider_determine_rate(hw, req, div_data->table, div_data->width,
drivers/clk/clk-versaclock3.c
527
div_data->flags);
drivers/clk/clk-versaclock3.c
534
const struct vc3_div_data *div_data = vc3->data;
drivers/clk/clk-versaclock3.c
537
value = divider_get_val(rate, parent_rate, div_data->table,
drivers/clk/clk-versaclock3.c
538
div_data->width, div_data->flags);
drivers/clk/clk-versaclock3.c
539
return regmap_update_bits(vc3->regmap, div_data->offs,
drivers/clk/clk-versaclock3.c
540
VC3_DIV_MASK(div_data->width) << div_data->shift,
drivers/clk/clk-versaclock3.c
541
value << div_data->shift);
drivers/clk/sunxi/clk-sunxi.c
731
static const struct div_data sun4i_axi_data __initconst = {
drivers/clk/sunxi/clk-sunxi.c
749
static const struct div_data sun8i_a23_axi_data __initconst = {
drivers/clk/sunxi/clk-sunxi.c
754
static const struct div_data sun4i_ahb_data __initconst = {
drivers/clk/sunxi/clk-sunxi.c
768
static const struct div_data sun4i_apb0_data __initconst = {
drivers/clk/sunxi/clk-sunxi.c
776
const struct div_data *data)
drivers/clk/ti/clkctrl.c
395
const struct omap_clkctrl_div_data *div_data = data->data;
drivers/clk/ti/clkctrl.c
404
div->flags = div_data->flags;
drivers/clk/ti/clkctrl.c
409
if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
drivers/clk/ti/clkctrl.c
410
div_data->max_div, div_flags,