ddiv
ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
struct ddiv cfg_ddiv = core->cfg.ddiv;
struct ddiv_clk *ddiv;
ddiv = devm_kzalloc(priv->dev, sizeof(*ddiv), GFP_KERNEL);
if (!ddiv)
ddiv->priv = priv;
ddiv->mon = cfg_ddiv.monbit;
div = &ddiv->div;
struct ddiv ddiv;
struct ddiv ddiv = dsi_div->ddiv;
div = readl(priv->base + ddiv.offset);
div >>= ddiv.shift;
div &= clk_div_mask(ddiv.width);
struct ddiv ddiv = dsi_div->ddiv;
shift = ddiv.shift;
val = readl(priv->base + ddiv.offset) | DDIV_DIVCTL_WEN(shift);
val &= ~(clk_div_mask(ddiv.width) << shift);
writel(val, priv->base + ddiv.offset);
clk_hw_data->ddiv = core->cfg.ddiv;
struct ddiv_clk *ddiv = to_ddiv_clock(divider);
struct rzv2h_cpg_priv *priv = ddiv->priv;
struct ddiv ddiv;
.cfg.ddiv = _ddiv_packed, \
.cfg.ddiv = _ddiv_packed, \
((struct ddiv){ \
((struct ddiv){ \
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift0, ddiv->width0) + 1;
div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift1, ddiv->width1) + 1;
exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
ddiv->shift2, ddiv->width2);
do_div(prate, ddiv->div);
prate *= ddiv->mult;
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate,
ddiv->width_gate, 1);
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate,
ddiv->width_gate, 0);
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift0, ddiv->width0,
lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift1, ddiv->width1,
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
struct lgm_clk_ddiv *ddiv;
ddiv = devm_kzalloc(dev, sizeof(*ddiv), GFP_KERNEL);
if (!ddiv)
ddiv->membase = ctx->membase;
ddiv->reg = list->reg;
ddiv->shift0 = list->shift0;
ddiv->width0 = list->width0;
ddiv->shift1 = list->shift1;
ddiv->width1 = list->width1;
ddiv->shift_gate = list->shift_gate;
ddiv->width_gate = list->width_gate;
ddiv->shift2 = list->ex_shift;
ddiv->width2 = list->ex_width;
ddiv->flags = list->div_flags;
ddiv->mult = 2;
ddiv->div = 5;
ddiv->hw.init = &init;
hw = &ddiv->hw;
calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
*ddiv = div - 2;
calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
*ddiv = 0x00000000;
sclk = calc_div(clk, idx, sclk, freq, ddiv);
info->ddiv |= 0x80000000;
info->ddiv |= div0 << 8;
info->ddiv |= div0;
nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x80003f3f, info->ddiv);
u32 ddiv;
calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv)
*ddiv = div - 2;
calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv)
*ddiv = 0x00000000;
sclk = calc_div(clk, idx, sclk, freq, ddiv);
info->ddiv |= 0x80000000;
info->ddiv |= div0;
nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv);
u32 ddiv;