drivers/gpu/drm/tidss/tidss_dispc.c

1443

dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,

drivers/gpu/drm/tidss/tidss_dispc.c

1608

dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],

drivers/gpu/drm/tidss/tidss_dispc.c

1627

dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],

drivers/gpu/drm/tidss/tidss_dispc.c

1780

dispc_vid_write(dispc, hw_plane, reg, c0);

drivers/gpu/drm/tidss/tidss_dispc.c

1793

dispc_vid_write(dispc, hw_plane, reg, c12);

drivers/gpu/drm/tidss/tidss_dispc.c

2005

dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,

drivers/gpu/drm/tidss/tidss_dispc.c

2012

dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,

drivers/gpu/drm/tidss/tidss_dispc.c

2021

dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);

drivers/gpu/drm/tidss/tidss_dispc.c

2028

dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);

drivers/gpu/drm/tidss/tidss_dispc.c

2207

dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);

drivers/gpu/drm/tidss/tidss_dispc.c

2208

dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);

drivers/gpu/drm/tidss/tidss_dispc.c

2209

dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);

drivers/gpu/drm/tidss/tidss_dispc.c

2210

dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);

drivers/gpu/drm/tidss/tidss_dispc.c

2212

dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,

drivers/gpu/drm/tidss/tidss_dispc.c

2218

dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,

drivers/gpu/drm/tidss/tidss_dispc.c

2221

dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,

drivers/gpu/drm/tidss/tidss_dispc.c

2224

dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,

drivers/gpu/drm/tidss/tidss_dispc.c

2234

dispc_vid_write(dispc, hw_plane,

drivers/gpu/drm/tidss/tidss_dispc.c

2236

dispc_vid_write(dispc, hw_plane,

drivers/gpu/drm/tidss/tidss_dispc.c

2238

dispc_vid_write(dispc, hw_plane,

drivers/gpu/drm/tidss/tidss_dispc.c

2240

dispc_vid_write(dispc, hw_plane,

drivers/gpu/drm/tidss/tidss_dispc.c

2243

dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,

drivers/gpu/drm/tidss/tidss_dispc.c

2250

dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,

drivers/gpu/drm/tidss/tidss_dispc.c

2267

dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,

drivers/gpu/drm/tidss/tidss_dispc.c

2294

dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,

drivers/gpu/drm/tidss/tidss_dispc.c

2302

dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,

drivers/gpu/drm/tidss/tidss_dispc.c

2349

dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);

drivers/gpu/drm/tidss/tidss_dispc.c

2406

dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);

drivers/gpu/drm/tidss/tidss_dispc.c

587

dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \

drivers/gpu/drm/tidss/tidss_dispc.c

694

dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);

drivers/gpu/drm/tidss/tidss_dispc.c

726

dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);