ddb - Linux

drivers/gpu/drm/i915/display/intel_cursor.c

624

const struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/intel_cursor.c

645

skl_cursor_ddb_reg_val(ddb));

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

100

const struct skl_ddb_entry *ddb,

drivers/gpu/drm/i915/display/intel_dbuf_bw.c

104

unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);

drivers/gpu/drm/i915/display/intel_display.c

7015

entries[pipe] = old_crtc_state->wm.skl.ddb;

drivers/gpu/drm/i915/display/intel_display.c

7053

if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,

drivers/gpu/drm/i915/display/intel_display.c

7057

entries[pipe] = new_crtc_state->wm.skl.ddb;

drivers/gpu/drm/i915/display/intel_display.c

7068

if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,

drivers/gpu/drm/i915/display/intel_display.c

7069

&old_crtc_state->wm.skl.ddb) &&

drivers/gpu/drm/i915/display/intel_display.c

7142

skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,

drivers/gpu/drm/i915/display/intel_display.c

7145

entries[pipe] = new_crtc_state->wm.skl.ddb;

drivers/gpu/drm/i915/display/intel_display_types.h

928

struct skl_ddb_entry ddb;

drivers/gpu/drm/i915/display/intel_plane.c

1020

struct skl_ddb_entry ddb[I915_MAX_PLANES];

drivers/gpu/drm/i915/display/intel_plane.c

1025

memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,

drivers/gpu/drm/i915/display/intel_plane.c

1030

while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {

drivers/gpu/drm/i915/display/intel_plane.c

888

struct skl_ddb_entry ddb[I915_MAX_PLANES],

drivers/gpu/drm/i915/display/intel_plane.c

909

ddb, I915_MAX_PLANES, plane_id) ||

drivers/gpu/drm/i915/display/intel_plane.c

915

ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];

drivers/gpu/drm/i915/display/skl_universal_plane.c

829

const struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/skl_universal_plane.c

855

skl_plane_ddb_reg_val(ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

1349

skl_check_wm_level(struct skl_wm_level *wm, const struct skl_ddb_entry *ddb)

drivers/gpu/drm/i915/display/skl_watermark.c

1351

if (wm->min_ddb_alloc > skl_ddb_entry_size(ddb))

drivers/gpu/drm/i915/display/skl_watermark.c

1358

const struct skl_ddb_entry *ddb)

drivers/gpu/drm/i915/display/skl_watermark.c

1361

wm->min_ddb_alloc_uv > skl_ddb_entry_size(ddb))

drivers/gpu/drm/i915/display/skl_watermark.c

1391

struct skl_ddb_entry *ddb, u64 data_rate)

drivers/gpu/drm/i915/display/skl_watermark.c

1410

iter->start = skl_ddb_entry_init(ddb, iter->start,

drivers/gpu/drm/i915/display/skl_watermark.c

1417

struct skl_ddb_entry *ddb, u64 data_rate)

drivers/gpu/drm/i915/display/skl_watermark.c

1419

_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc, ddb, data_rate);

drivers/gpu/drm/i915/display/skl_watermark.c

1426

struct skl_ddb_entry *ddb, u64 data_rate)

drivers/gpu/drm/i915/display/skl_watermark.c

1429

_skl_allocate_plane_ddb(iter, wm->min_ddb_alloc_uv, ddb, data_rate);

drivers/gpu/drm/i915/display/skl_watermark.c

1440

const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];

drivers/gpu/drm/i915/display/skl_watermark.c

1484

const struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/skl_watermark.c

1487

if (wm->wm[level].min_ddb_alloc > skl_ddb_entry_size(ddb)) {

drivers/gpu/drm/i915/display/skl_watermark.c

1524

struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/skl_watermark.c

1541

ddb, crtc_state->rel_data_rate[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.c

1544

ddb, crtc_state->rel_data_rate[plane_id]);

drivers/gpu/drm/i915/display/skl_watermark.c

1561

const struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/skl_watermark.c

1570

skl_check_wm_level_nv12(&wm->wm[level], ddb_y, ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

1572

skl_check_wm_level(&wm->wm[level], ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

1587

const struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/skl_watermark.c

1602

skl_check_wm_level(&wm->trans_wm, ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

1605

skl_check_wm_level(&wm->sagv.wm0, ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

1609

skl_check_wm_level(&wm->sagv.trans_wm, ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

2418

bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,

drivers/gpu/drm/i915/display/skl_watermark.c

2426

skl_ddb_entries_overlap(ddb, &entries[i]))

drivers/gpu/drm/i915/display/skl_watermark.c

3050

memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));

drivers/gpu/drm/i915/display/skl_watermark.c

3053

struct skl_ddb_entry *ddb =

drivers/gpu/drm/i915/display/skl_watermark.c

3066

plane_id, ddb, ddb_y,

drivers/gpu/drm/i915/display/skl_watermark.c

3069

skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

3070

skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);

drivers/gpu/drm/i915/display/skl_watermark.c

3082

crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;

drivers/gpu/drm/i915/display/skl_watermark.c

3083

crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;

drivers/gpu/drm/i915/display/skl_watermark.c

3087

skl_ddb_dbuf_slice_mask(display, &crtc_state->wm.skl.ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

3092

dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,

drivers/gpu/drm/i915/display/skl_watermark.c

3093

dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,

drivers/gpu/drm/i915/display/skl_watermark.c

3763

entries[crtc->pipe] = crtc_state->wm.skl.ddb;

drivers/gpu/drm/i915/display/skl_watermark.c

3776

if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,

drivers/gpu/drm/i915/display/skl_watermark.c

3816

memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

3843

memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));

drivers/gpu/drm/i915/display/skl_watermark.c

3845

memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));

drivers/gpu/drm/i915/display/skl_watermark.c

3911

struct skl_ddb_entry ddb[I915_MAX_PLANES];

drivers/gpu/drm/i915/display/skl_watermark.c

3931

skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

3973

&hw->ddb[plane->id],

drivers/gpu/drm/i915/display/skl_watermark.c

411

struct skl_ddb_entry *ddb)

drivers/gpu/drm/i915/display/skl_watermark.c

416

ddb->start = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

417

ddb->end = 0;

drivers/gpu/drm/i915/display/skl_watermark.c

421

ddb->start = (ffs(slice_mask) - 1) * slice_size;

drivers/gpu/drm/i915/display/skl_watermark.c

422

ddb->end = fls(slice_mask) * slice_size;

drivers/gpu/drm/i915/display/skl_watermark.c

424

WARN_ON(ddb->start >= ddb->end);

drivers/gpu/drm/i915/display/skl_watermark.c

425

WARN_ON(ddb->end > DISPLAY_INFO(display)->dbuf.size);

drivers/gpu/drm/i915/display/skl_watermark.c

43

struct skl_ddb_entry ddb[I915_MAX_PIPES];

drivers/gpu/drm/i915/display/skl_watermark.c

430

struct skl_ddb_entry ddb;

drivers/gpu/drm/i915/display/skl_watermark.c

437

skl_ddb_entry_for_slices(display, slice_mask, &ddb);

drivers/gpu/drm/i915/display/skl_watermark.c

439

return ddb.start;

drivers/gpu/drm/i915/display/skl_watermark.c

540

skl_ddb_entry_init(&new_dbuf_state->ddb[pipe], 0, 0);

drivers/gpu/drm/i915/display/skl_watermark.c

556

skl_ddb_entry_init(&new_dbuf_state->ddb[pipe],

drivers/gpu/drm/i915/display/skl_watermark.c

562

skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],

drivers/gpu/drm/i915/display/skl_watermark.c

563

&new_dbuf_state->ddb[pipe]))

drivers/gpu/drm/i915/display/skl_watermark.c

578

crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;

drivers/gpu/drm/i915/display/skl_watermark.c

579

crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;

drivers/gpu/drm/i915/display/skl_watermark.c

585

old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end,

drivers/gpu/drm/i915/display/skl_watermark.c

586

new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end,

drivers/gpu/drm/i915/display/skl_watermark.c

679

struct skl_ddb_entry *ddb,

drivers/gpu/drm/i915/display/skl_watermark.c

688

skl_ddb_entry_init_from_hw(ddb, val);

drivers/gpu/drm/i915/display/skl_watermark.c

693

skl_ddb_entry_init_from_hw(ddb, val);

drivers/gpu/drm/i915/display/skl_watermark.c

710

struct skl_ddb_entry *ddb,

drivers/gpu/drm/i915/display/skl_watermark.c

728

&ddb[plane_id],

drivers/gpu/drm/i915/display/skl_watermark.h

33

bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,

drivers/media/pci/ddbridge/ddbridge-core.c

107

static struct ddb *ddbs[DDB_MAX_ADAPTER];

drivers/media/pci/ddbridge/ddbridge-core.c

113

struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,

drivers/media/pci/ddbridge/ddbridge-core.c

125

struct ddb *dev = io->port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

1337

static int dvb_register_adapters(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

1415

static void dvb_unregister_adapters(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

142

static void ddb_set_dma_tables(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

160

static void ddb_redirect_dma(struct ddb *dev,

drivers/media/pci/ddbridge/ddbridge-core.c

1721

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

1767

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

1838

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2046

int ddb_ports_attach(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

2085

void ddb_ports_detach(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

2130

struct ddb *dev = input->port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2168

struct ddb *dev = input->port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2199

struct ddb *dev = output->port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

220

struct ddb *idev = ddbs[(i >> 4) & 0x3f];

drivers/media/pci/ddbridge/ddbridge-core.c

222

struct ddb *pdev = ddbs[(p >> 4) & 0x3f];

drivers/media/pci/ddbridge/ddbridge-core.c

2273

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2304

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2329

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2344

struct ddb *dev = port->dev;

drivers/media/pci/ddbridge/ddbridge-core.c

2356

void ddb_ports_init(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

2447

void ddb_ports_release(struct ddb *dev)

drivers/media/pci/ddbridge/ddbridge-core.c

2495

static void irq_handle_msg(struct ddb *dev, u32 s)

drivers/media/pci/ddbridge/ddbridge-core.c

2501

static void irq_handle_io(struct ddb *dev, u32 s)

drivers/media/pci/ddbridge/ddbridge-core.c

2512

struct ddb *dev = (struct ddb *)dev_id;

drivers/media/pci/ddbridge/ddbridge-core.c

2530

struct ddb *dev = (struct ddb *)dev_id;

drivers/media/pci/ddbridge/ddbridge-core.c

2548

struct ddb *dev = (struct ddb *)dev_id;

drivers/media/pci/ddbridge/ddbridge-core.c

2572

static int reg_wait(struct ddb *dev, u32 reg, u32 bit)

drivers/media/pci/ddbridge/ddbridge-core.c

2584

static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf,

drivers/media/pci/ddbridge/ddbridge-core.c

2666

int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len)

drivers/media/pci/ddbridge/ddbridge-core.c

2686

struct ddb *dev = file->private_data;

drivers/media/pci/ddbridge/ddbridge-core.c

2694

struct ddb *dev = ddbs[iminor(inode)];

drivers/media/pci/ddbridge/ddbridge-core.c

2705

struct ddb *dev = file->private_data;

drivers/media/pci/ddbridge/ddbridge-core.c

2721

const struct ddb *dev = dev_get_drvdata(device);