drivers/gpu/drm/tidss/tidss_dispc.c

613

static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport)

drivers/gpu/drm/tidss/tidss_dispc.c

615

dispc_irq_t vp_stat = 0;

drivers/gpu/drm/tidss/tidss_dispc.c

629

static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport)

drivers/gpu/drm/tidss/tidss_dispc.c

645

static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane)

drivers/gpu/drm/tidss/tidss_dispc.c

647

dispc_irq_t vid_stat = 0;

drivers/gpu/drm/tidss/tidss_dispc.c

655

static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane)

drivers/gpu/drm/tidss/tidss_dispc.c

665

static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

674

u32 hw_videoport, dispc_irq_t vpstat)

drivers/gpu/drm/tidss/tidss_dispc.c

681

static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

690

u32 hw_plane, dispc_irq_t vidstat)

drivers/gpu/drm/tidss/tidss_dispc.c

697

static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

706

u32 hw_videoport, dispc_irq_t vpstat)

drivers/gpu/drm/tidss/tidss_dispc.c

713

static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

722

u32 hw_plane, dispc_irq_t vidstat)

drivers/gpu/drm/tidss/tidss_dispc.c

730

dispc_irq_t mask)

drivers/gpu/drm/tidss/tidss_dispc.c

737

dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc)

drivers/gpu/drm/tidss/tidss_dispc.c

739

dispc_irq_t stat = 0;

drivers/gpu/drm/tidss/tidss_dispc.c

753

static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc)

drivers/gpu/drm/tidss/tidss_dispc.c

755

dispc_irq_t stat = 0;

drivers/gpu/drm/tidss/tidss_dispc.c

764

void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)

drivers/gpu/drm/tidss/tidss_dispc.c

766

dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);

drivers/gpu/drm/tidss/tidss_dispc.c

783

static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

792

u32 hw_videoport, dispc_irq_t vpstat)

drivers/gpu/drm/tidss/tidss_dispc.c

799

static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

809

u32 hw_plane, dispc_irq_t vidstat)

drivers/gpu/drm/tidss/tidss_dispc.c

817

static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

826

u32 hw_videoport, dispc_irq_t vpstat)

drivers/gpu/drm/tidss/tidss_dispc.c

833

static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,

drivers/gpu/drm/tidss/tidss_dispc.c

843

u32 hw_plane, dispc_irq_t vidstat)

drivers/gpu/drm/tidss/tidss_dispc.c

852

void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)

drivers/gpu/drm/tidss/tidss_dispc.c

874

dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)

drivers/gpu/drm/tidss/tidss_dispc.c

876

dispc_irq_t status = 0;

drivers/gpu/drm/tidss/tidss_dispc.c

890

static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)

drivers/gpu/drm/tidss/tidss_dispc.c

892

dispc_irq_t enable = 0;

drivers/gpu/drm/tidss/tidss_dispc.c

905

dispc_irq_t mask)

drivers/gpu/drm/tidss/tidss_dispc.c

909

dispc_irq_t old_mask;

drivers/gpu/drm/tidss/tidss_dispc.c

948

dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)

drivers/gpu/drm/tidss/tidss_dispc.c

965

void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)

drivers/gpu/drm/tidss/tidss_dispc.h

109

void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);

drivers/gpu/drm/tidss/tidss_dispc.h

110

dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);

drivers/gpu/drm/tidss/tidss_drv.h

43

dispc_irq_t irq_mask; /* enabled irqs */

drivers/gpu/drm/tidss/tidss_irq.c

60

dispc_irq_t irqstatus;

drivers/gpu/drm/tidss/tidss_irq.h

42

static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch)

drivers/gpu/drm/tidss/tidss_irq.h

47

static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane)