drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1014

const struct dml_display_cfg_st *disp_cfg,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1021

populate_odm_factors(ctx, disp_cfg, mapping, state, ctx->pipe_combine_scratch.odm_factors);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1023

populate_mpc_factors_for_stream(ctx, disp_cfg, mapping, state,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1035

bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1052

ctx, state, disp_cfg, mapping, existing_state);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1070

ODMMode = (unsigned int *)disp_cfg->hw.ODMMode;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1071

DPPPerSurface = disp_cfg->hw.DPPPerSurface;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

1154

if (!validate_pipe_assignment(ctx, state, disp_cfg, mapping))

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

179

static bool validate_pipe_assignment(const struct dml2_context *ctx, const struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, const struct dml2_dml_to_dc_pipe_mapping *mapping)

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

793

const struct dml_display_cfg_st *disp_cfg,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

807

mpc_factor = (unsigned int)disp_cfg->hw.DPPPerSurface[cfg_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

851

const struct dml_display_cfg_st *disp_cfg,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

860

switch (disp_cfg->hw.ODMMode[cfg_idx]) {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

922

const struct dml_display_cfg_st *disp_cfg,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

935

get_target_mpc_factor(ctx, state, disp_cfg, mapping, status, state->streams[stream_idx], i) : 1;

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

940

const struct dml_display_cfg_st *disp_cfg,

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c

950

ctx, state, disp_cfg, mapping, state->streams[i]);

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h

50

bool dml2_map_dc_pipes(struct dml2_context *ctx, struct dc_state *state, const struct dml_display_cfg_st *disp_cfg, struct dml2_dml_to_dc_pipe_mapping *mapping, const struct dc_state *existing_state);

drivers/gpu/drm/kmb/kmb_drv.h

59

struct disp_cfg init_disp_cfg[KMB_MAX_PLANES];

drivers/gpu/drm/kmb/kmb_plane.c

100

struct disp_cfg init_disp_cfg;

drivers/gpu/drm/kmb/kmb_plane.c

360

struct disp_cfg *init_disp_cfg;

drivers/gpu/drm/kmb/kmb_plane.c

74

struct disp_cfg init_disp_cfg;