dib8000_read_word
dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));
dyn_gain = dib8000_read_word(state, 390);
reg = dib8000_read_word(state, 922) & (0x3 << 2);
(dib8000_read_word(state, 923) & 0xffe3) |
agc = dib8000_read_word(state, 390);
dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
reg = dib8000_read_word(state, 1947)&0xff00;
reg = dib8000_read_word(state, 1920);
reg = dib8000_read_word(state, 1798) &
reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
reg = dib8000_read_word(state, 1800) &
reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
reg = dib8000_read_word(state, 1802) &
reg_1287 = dib8000_read_word(state, 1287);
u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
reg_1287 = dib8000_read_word(state, 1287);
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
outreg = dib8000_read_word(state, 1286) &
n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
n_empty = dib8000_read_word(state, 1984)&0x1;
read_word = dib8000_read_word(state, 1987);
word = dib8000_read_word(state, apb_address);
i = ((dib8000_read_word(state, 921) >> 12)&0x3);
word = dib8000_read_word(state, 924+i);
word = (dib8000_read_word(state, 921) &
en_cur_state = dib8000_read_word(state, 1922);
val = dib8000_read_word(state, 403);
val = dib8000_read_word(state, 404);
reg_1 = dib8000_read_word(state, 1);
dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */
dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */
dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */
dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */
dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */
tmp = dib8000_read_word(state, 1);
dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */
dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */
dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */
dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */
dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */
dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */
dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */
value = dib8000_read_word(state, 0);
dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */
dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */
value = dib8000_read_word(state, 0);
dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
u16 irq_pending = dib8000_read_word(state, 1284);
tmp = dib8000_read_word(state, 771);
i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */
dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));
return dib8000_read_word(state, 570);
return dib8000_read_word(state, 568);
reg = dib8000_read_word(state, 274) & 0xfff0;
reg = dib8000_read_word(state, 1280);
dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
state->agc1_max = dib8000_read_word(state, 108);
state->agc1_min = dib8000_read_word(state, 109);
state->agc2_max = dib8000_read_word(state, 110);
state->agc2_min = dib8000_read_word(state, 111);
agc1 = dib8000_read_word(state, 388);
agc2 = dib8000_read_word(state, 389);
corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));
corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));
corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
state->found_guard = dib8000_read_word(state, 572) & 0x3;
state->found_guard = dib8000_read_word(state, 570) & 0x3;
locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON);
if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
val = dib8000_read_word(state, 572);
val = dib8000_read_word(state, 570);
val = dib8000_read_word(state, 505);
val = dib8000_read_word(state, 493 + i) & 0x0f;
val = dib8000_read_word(state, 499 + i) & 0x3;
val = dib8000_read_word(state, 481 + i);
val = dib8000_read_word(state, 487 + i);
lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
*ber = (dib8000_read_word(state, 562) << 16) |
dib8000_read_word(state, 563);
*ber = (dib8000_read_word(state, 560) << 16) |
dib8000_read_word(state, 561);
*unc = dib8000_read_word(state, 567);
*unc = dib8000_read_word(state, 565);
val = 65535 - dib8000_read_word(state, 390);
val = dib8000_read_word(state, 542);
val = dib8000_read_word(state, 544);
val = dib8000_read_word(state, 543);
val = dib8000_read_word(state, 545);
u16 nud = dib8000_read_word(state, 298);
smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
val = dib8000_read_word(state, per_layer_regs[i].ber);
val = dib8000_read_word(state, per_layer_regs[i].per);
u16 val = dib8000_read_word(st, 299) & 0xffef;
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;
tmp = dib8000_read_word(state, 903);
reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
u16 reg, reg_907 = dib8000_read_word(state, 907);
u16 reg_908 = dib8000_read_word(state, 908);
reg = dib8000_read_word(state, 1925);
reg = dib8000_read_word(state, 1925);
reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
reg = dib8000_read_word(state, 1925);
reg = dib8000_read_word(state, 1857);
reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
reg_1857 = dib8000_read_word(state, 1857);
while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
reg_1856 = dib8000_read_word(state, 1856);
dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */
st->cfg.gpio_dir = dib8000_read_word(st, 1029);
st->cfg.gpio_val = dib8000_read_word(st, 1030);