dib7000m_read_word
value = dib7000m_read_word(state, 0);
dib7000m_read_word(state, 537);
u16 irq_pending = dib7000m_read_word(state, reg);
if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
state->revision = dib7000m_read_word(state, 897);
if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
u16 tps = dib7000m_read_word(state,480);
u16 lock = dib7000m_read_word(state, 535);
*ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527);
*unc = dib7000m_read_word(state, 534);
u16 val = dib7000m_read_word(state, 390);
u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef;
smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
u16 reg_913 = dib7000m_read_word(state, 913),
reg_914 = dib7000m_read_word(state, 914);
dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
agc = dib7000m_read_word(state, 390);
return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
dyn_gain = dib7000m_read_word(state, 390);
dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
u16 cfg_72 = dib7000m_read_word(state, 72);
agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */
dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */