dib3000mc_write_word
dib3000mc_write_word(state, 23, (u16) (timf >> 16));
dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff);
dib3000mc_write_word(state, 51, reg_51);
dib3000mc_write_word(state, 52, reg_52);
dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0));
dib3000mc_write_word(state, 245, 0);
dib3000mc_write_word(state, 1040, 0x3);
ret |= dib3000mc_write_word(state, 244, outreg);
ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/
ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */
ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */
dib3000mc_write_word(state, reg, bw_cfg[reg - 6]);
dib3000mc_write_word(state, 12, 0x0000);
dib3000mc_write_word(state, 13, 0x03e8);
dib3000mc_write_word(state, 14, 0x0000);
dib3000mc_write_word(state, 15, 0x03f2);
dib3000mc_write_word(state, 16, 0x0001);
dib3000mc_write_word(state, 17, 0xb0d0);
dib3000mc_write_word(state, 18, 0x0393);
dib3000mc_write_word(state, 19, 0x8700);
dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]);
dib3000mc_write_word(state, i, impulse_noise_val[i-58]);
dib3000mc_write_word(state, 58, 0x3b);
dib3000mc_write_word(state, 84, 0x00);
dib3000mc_write_word(state, 85, 0x8200);
dib3000mc_write_word(state, 34, 0x1294);
dib3000mc_write_word(state, 35, 0x1ff8);
dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10));
dib3000mc_write_word(state, 1027, 0x8000);
dib3000mc_write_word(state, 1027, 0x0000);
dib3000mc_write_word(state, 140, 0x0000);
dib3000mc_write_word(state, 1031, 0);
dib3000mc_write_word(state, 139, 0x0000);
dib3000mc_write_word(state, 141, 0x0000);
dib3000mc_write_word(state, 175, 0x0002);
dib3000mc_write_word(state, 1032, 0x0000);
dib3000mc_write_word(state, 139, 0x0001);
dib3000mc_write_word(state, 141, 0x0000);
dib3000mc_write_word(state, 175, 0x0000);
dib3000mc_write_word(state, 1032, 0x012C);
dib3000mc_write_word(state, 1033, 0x0000);
dib3000mc_write_word(state, 1037, 0x3130);
dib3000mc_write_word(state, 33, (5 << 0));
dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0));
dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0));
dib3000mc_write_word(state, 111, 0x00);
dib3000mc_write_word(state, 111, 0x02);
dib3000mc_write_word(state, 50, 0x8000);
dib3000mc_write_word(state, 53, 0x87);
dib3000mc_write_word(state, 54, 0x87);
dib3000mc_write_word(state, 36, state->cfg->max_time);
dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12) | (0x1d << 0));
dib3000mc_write_word(state, 38, state->cfg->pwm3_value);
dib3000mc_write_word(state, 39, state->cfg->ln_adc_level);
dib3000mc_write_word(state, 40, 0x0179);
dib3000mc_write_word(state, 41, 0x03f0);
dib3000mc_write_word(state, 42, agc->agc1_max);
dib3000mc_write_word(state, 43, agc->agc1_min);
dib3000mc_write_word(state, 44, agc->agc2_max);
dib3000mc_write_word(state, 45, agc->agc2_min);
dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
dib3000mc_write_word(state, 110, 3277);
dib3000mc_write_word(state, 26, 0x6680);
dib3000mc_write_word(state, 1, 4);
dib3000mc_write_word(state, 2, 4);
dib3000mc_write_word(state, 3, 0x1000);
dib3000mc_write_word(state, 5, 1);
dib3000mc_write_word(state, 4, 0x814);
dib3000mc_write_word(state, 21, (1 << 9) | 0x164);
dib3000mc_write_word(state, 22, 0x463d);
dib3000mc_write_word(state, 120, 0x200f);
dib3000mc_write_word(state, 134, 0);
dib3000mc_write_word(state, 195, 0x10);
dib3000mc_write_word(state, 180, 0x2FF0);
dib3000mc_write_word(state, 769, (1 << 7) );
dib3000mc_write_word(state, 1031, 0xFFFF);
dib3000mc_write_word(state, 1032, 0xFFFF);
dib3000mc_write_word(state, 1033, 0xFFF0);
dib3000mc_write_word(state, reg, cfg[reg - 129]);
dib3000mc_write_word(state, 100, (16 << 6) + 9);
dib3000mc_write_word(state, 100, (11 << 6) + 6);
dib3000mc_write_word(state, 100, (16 << 6) + 9);
dib3000mc_write_word(state, 1027, 0x0800);
dib3000mc_write_word(state, 1027, 0x0000);
dib3000mc_write_word(state, 26, 0x6680);
dib3000mc_write_word(state, 29, 0x1273);
dib3000mc_write_word(state, 33, 5);
dib3000mc_write_word(state, 133, 15564);
dib3000mc_write_word(state, 12 , 0x0);
dib3000mc_write_word(state, 13 , 0x3e8);
dib3000mc_write_word(state, 14 , 0x0);
dib3000mc_write_word(state, 15 , 0x3f2);
dib3000mc_write_word(state, 93,0);
dib3000mc_write_word(state, 94,0);
dib3000mc_write_word(state, 95,0);
dib3000mc_write_word(state, 96,0);
dib3000mc_write_word(state, 97,0);
dib3000mc_write_word(state, 98,0);
dib3000mc_write_word(state, 0, value);
dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4));
dib3000mc_write_word(state, 181, value);
dib3000mc_write_word(state, 180, value);
dib3000mc_write_word(state, 0, value | (1 << 9));
dib3000mc_write_word(state, 0, value);
dib3000mc_write_word(state, 0, reg | (1 << 8));
dib3000mc_write_word(state, 0, reg);
dib3000mc_write_word(state, 29, 0x1273);
dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift
dib3000mc_write_word(state, 29, 0x1073);
dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift
dib3000mc_write_word(state, 26, 38528);
dib3000mc_write_word(state, 33, 8);
dib3000mc_write_word(state, 26, 30336);
dib3000mc_write_word(state, 33, 6);
dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0);
return dib3000mc_write_word(state, 206, tmp);
dib3000mc_write_word(dmcst, 1024, (new_addr << 3) | 0x1);
dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3);
dib3000mc_write_word(st, 1037, 0x3130);