dib0090_read_reg
dprintk("total RF gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x2a));
dprintk("total BB gain: %ddB, step: %d\n", (u32) cfg[0], dib0090_read_reg(state, 0x33));
u16 adc_val = dib0090_read_reg(state, 0x1d);
dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)
dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)
e2 = dib0090_read_reg(state, 0x26);
e4 = dib0090_read_reg(state, 0x28);
cal = (dib0090_read_reg(state, 0x22) >> 6) & 0x3ff;
if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
dprintk("Pll lock : %d\n", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
state->adc_diff = dib0090_read_reg(state, 0x1d);
state->adc_diff -= dib0090_read_reg(state, 0x1d);
reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
state->wbdmux = dib0090_read_reg(state, 0x10);
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)
dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)
state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
dib0090_read_reg(state, 0x40);
dib0090_read_reg(state, 0x40);
state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
state->wbdmux = dib0090_read_reg(state, 0x10);
state->bias = dib0090_read_reg(state, 0x13);
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
tmp = dib0090_read_reg(state, 0x39);
dprintk("FBDIV: %d, Rest: %d\n", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
dprintk("Num: %d, Den: %d, SD: %d\n", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
(u32) dib0090_read_reg(state, 0x1c) & 0x3);
v = dib0090_read_reg(state, 0x1a);
PllCfg = dib0090_read_reg(state, 0x21);
v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));