dib0070_write_reg
dib0070_write_reg(state, 0x02, tmp);
dib0070_write_reg(state, 0x17, value & 0xfffc);
dib0070_write_reg(state, 0x01, tmp | (60 << 9));
dib0070_write_reg(state, 0x17, value);
dib0070_write_reg(state, 0x0f, 0xed10);
dib0070_write_reg(state, 0x17, 0x0034);
dib0070_write_reg(state, 0x18, 0x0032);
dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
dib0070_write_reg(state, 0x18, 0x07ff);
return dib0070_write_reg(state, 0x15, lo5);
dib0070_write_reg(state, 0x1b, 0xff00);
dib0070_write_reg(state, 0x1a, 0x0000);
dib0070_write_reg(state, 0x1b, 0x4112);
dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
dib0070_write_reg(state, 0x1a, 0x0009);
dib0070_write_reg(state, 0x17, 0x30);
dib0070_write_reg(state, 0x11, (u16)FBDiv);
dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
dib0070_write_reg(state, 0x13, (u16) Rest);
dib0070_write_reg(state, 0x1d, 0xFFFF);
dib0070_write_reg(state, 0x20,
dib0070_write_reg(state, 0x0f,
dib0070_write_reg(state, 0x0f,
dib0070_write_reg(state, 0x06, 0x3fff);
dib0070_write_reg(state, 0x07,
dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
dib0070_write_reg(state, 0x0d, 0x0d80);
dib0070_write_reg(state, 0x18, 0x07ff);
dib0070_write_reg(state, 0x17, 0x0033);
return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
dib0070_write_reg(state, 0x18, 0x07ff);
dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
dib0070_write_reg(state, 0x20, tuner_en);
dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
dib0070_write_reg(state, 0x10, r);
dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));
dib0070_write_reg(state, 0x02, r | (1 << 5));
dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);