drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1204

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2476

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3041

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3259

struct dce_hwseq *hws = params->dsc_pg_status_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3308

struct dce_hwseq *hws = params->dpp_pg_control_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3318

struct dce_hwseq *hws = params->hubp_pg_control_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3344

struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3356

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3446

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4335

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4387

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4401

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4415

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

742

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/dc.h

1035

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/dc.h

1886

struct dce_hwseq *hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

138

static void dce_disable_sram_shut_down(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

145

static void dce_underlay_clock_enable(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

163

void dce_clock_gating_power_up(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

175

void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

40

void dce_enable_fe_clock(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

53

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

97

void dce_set_blender_mode(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1286

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1290

void dce_enable_fe_clock(struct dce_hwseq *hwss,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1297

void dce_set_blender_mode(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1306

void dce_clock_gating_power_up(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1309

void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1266

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1284

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1705

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2062

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2649

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3023

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3132

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3285

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

199

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

255

bool dce121_xgmi_enabled(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.h

34

bool dce121_xgmi_enabled(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c

278

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1001

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1053

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1080

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1100

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1130

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1489

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1536

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1567

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1601

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1618

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1810

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1997

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2200

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

260

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2695

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2721

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2764

static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2783

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3032

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3259

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3388

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3426

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3613

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3679

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3692

void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

4083

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

876

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

898

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

940

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

102

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

106

struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

121

void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

94

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

98

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1112

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1276

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1680

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1906

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1931

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2050

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2250

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2491

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2615

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2630

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2664

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2686

int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2768

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2922

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

310

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3152

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

359

void dcn20_dccg_init(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

368

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

396

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

463

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

540

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

622

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

700

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

824

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

100

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

103

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

107

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

126

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

134

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

140

void dcn20_dccg_init(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

141

int dcn20_init_sys_ctx(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h

97

struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

110

static void plane_address_in_gpu_space_to_uma(struct dce_hwseq *hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

141

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

171

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

205

static void read_mmhub_vm_setup(struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

230

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

382

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

533

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

600

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

88

static bool gpu_addr_to_uma(struct dce_hwseq *hwseq,

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

54

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

68

int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h

33

int dcn21_init_sys_ctx(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

321

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

647

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

102

void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

159

void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

45

void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h

31

void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h

32

void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h

33

void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

46

void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

54

void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

62

void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.c

70

void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

32

void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

33

void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

34

void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn303/dcn303_hwseq.h

35

void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

116

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

282

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

346

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

461

void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

500

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

632

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

674

void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

74

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

36

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

41

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

49

void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

50

int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h

59

void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

227

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

297

void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

371

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

401

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

458

void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

546

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

36

void dcn314_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

38

void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

44

void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

46

void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h

50

void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1203

struct dce_hwseq *hws = stream->ctx->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1242

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1259

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1324

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

138

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1508

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1543

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1564

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1599

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1661

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

167

void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

533

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

71

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

732

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

793

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

107

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

34

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

39

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

42

void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h

78

void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

128

void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

137

void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

145

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

488

void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

499

void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

510

void dcn35_hdmistream_root_clock_control(struct dce_hwseq *hws, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

521

void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

642

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

80

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

915

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

36

void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

38

void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

40

void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

42

void dcn35_hdmistream_root_clock_control(struct dce_hwseq *hws, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

44

void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

46

void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

48

void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

87

void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h

89

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1057

void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

144

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1839

struct dce_hwseq *hws = link->dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2155

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2214

struct dce_hwseq *hws)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2239

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2369

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2519

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2682

struct dce_hwseq *hwseq = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2812

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3061

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3152

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3624

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3635

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3696

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

808

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

57

void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

64

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

49

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1257

void (*update_dchub)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1353

int (*init_sys_ctx)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1356

void (*init_vm_ctx)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1508

void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2172

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2190

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2195

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2200

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

48

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

606

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

612

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

626

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

637

struct dce_hwseq *hws;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

123

void (*disable_vga)(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

133

void (*enable_power_gating_plane)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

136

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

140

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

144

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

147

struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

150

void (*dpp_pg_control)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

153

void (*hubp_pg_control)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

156

void (*dsc_pg_control)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

159

bool (*dsc_pg_status)(struct dce_hwseq *hws,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

189

void (*dccg_init)(struct dce_hwseq *hws);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

198

void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

209

void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

69

struct dce_hwseq;

drivers/gpu/drm/amd/display/dc/inc/resource.h

101

struct dce_hwseq *(*create_hwseq)(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

520

static struct dce_hwseq *dce100_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

523

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1140

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

563

static struct dce_hwseq *dce110_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

566

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

540

static struct dce_hwseq *dce112_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

543

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

814

static struct dce_hwseq *dce120_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

817

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

828

static struct dce_hwseq *dce121_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

831

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

638

static struct dce_hwseq *dce60_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

641

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

644

static struct dce_hwseq *dce80_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

647

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

874

static struct dce_hwseq *dcn10_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

877

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1060

struct dce_hwseq *dcn20_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1063

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1261

struct dce_hwseq *hws = dc->hwseq;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

73

struct dce_hwseq *dcn20_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

912

static struct dce_hwseq *dcn201_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

915

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1200

static struct dce_hwseq *dcn21_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1203

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1181

static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1183

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1048

static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1050

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

591

static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

593

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

575

static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

577

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1458

static struct dce_hwseq *dcn31_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1461

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1518

static struct dce_hwseq *dcn314_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1521

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1460

static struct dce_hwseq *dcn31_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1463

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1455

static struct dce_hwseq *dcn31_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1458

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1470

static struct dce_hwseq *dcn32_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1473

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1445

static struct dce_hwseq *dcn321_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1448

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1521

static struct dce_hwseq *dcn35_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1524

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1501

static struct dce_hwseq *dcn351_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1504

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1508

static struct dce_hwseq *dcn36_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1511

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1455

static struct dce_hwseq *dcn401_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1458

struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1447

static struct dce_hwseq *dcn42_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1450

struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1427

static struct dce_hwseq *dcn42b_hwseq_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1430

struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);