drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

201

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

217

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

40

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

520

const struct dccg_mask *dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

548

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

40

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

71

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

87

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h

35

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

147

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

163

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

39

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h

33

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

103

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

119

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

128

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

144

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

38

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

58

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

64

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

38

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

62

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

78

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h

63

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

40

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

954

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

970

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

169

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

418

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

42

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

434

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

206

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

39

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

430

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

446

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

123

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2785

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2805

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

39

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

248

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

1004

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

49

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

902

if (dccg_dcn->dccg_mask->SYMCLKE_FE_ROOT_GATE_DISABLE) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

941

if (dccg_dcn->dccg_mask->SYMCLKE_FE_ROOT_GATE_DISABLE) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

988

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

241

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

19

dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

350

const struct dccg_mask *dccg_mask)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

366

dccg_dcn->dccg_mask = dccg_mask;

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

269

const struct dccg_mask *dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2583

pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

679

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1224

pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

559

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1554

pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

233

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2599

pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

664

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1586

pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

594

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1320

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1492

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1264

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1424

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2215

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

709

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2134

pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

716

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2167

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

708

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2039

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

703

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2526

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

562

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2019

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

552

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2172

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

566

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2144

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

546

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2142

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

553

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2229

pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

532

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2217

pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

487

static const struct dccg_mask dccg_mask = {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2169

pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

511

static const struct dccg_mask dccg_mask = {