devm_clk_bulk_get_optional
EXPORT_SYMBOL_GPL(devm_clk_bulk_get_optional);
err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
ret = devm_clk_bulk_get_optional(madera->dev, ARRAY_SIZE(madera->mclk),
ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks);
ret = devm_clk_bulk_get_optional(&pdev->dev,
ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks,
ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS,
return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS,
retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks);
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
return devm_clk_bulk_get_optional(dev, num, qmp->clks);
ret = devm_clk_bulk_get_optional(combophy->dev, 1, combophy->clks + combophy->num_clks);
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
return devm_clk_bulk_get_optional(dev, DSP_RPROC_CLK_MAX, clks);
ret = devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks);
return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
ret = devm_clk_bulk_get_optional(dev, BULK_CLKS_CNT, clks);
int __must_check devm_clk_bulk_get_optional(struct device *dev, int num_clks,
ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk),