drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

149

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

223

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

228

rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

250

dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

254

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

258

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

262

dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

265

dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

276

vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

289

dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

301

dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

313

dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

324

dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

336

dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

349

dcn42b_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

359

dcn351_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

361

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

368

struct clk_mgr_internal *clk_mgr = dcn401_clk_mgr_construct(ctx, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

386

dcn42_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h

45

int dce12_get_dp_ref_freq_khz(struct clk_mgr *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

109

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

119

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

122

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

123

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

155

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

168

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

169

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

172

dccg->funcs->otg_drop_pixel(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

173

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

175

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

176

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

185

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

199

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

201

dccg->funcs->otg_add_pixel(dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

203

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

399

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

535

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

549

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

29

void dcn2_update_clocks(struct clk_mgr *dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h

44

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

182

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

192

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h

32

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

111

clk_mgr->dccg->ref_dppclk = ref_dpp_clk;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

122

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

125

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

126

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

710

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

725

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h

47

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

530

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

541

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.h

94

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

686

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

696

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.h

48

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

684

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

694

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h

52

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

801

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

811

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h

64

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

617

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

627

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h

45

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

592

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

602

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h

45

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1163

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

1180

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

270

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

287

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

298

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

331

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

352

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

355

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

356

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

386

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

399

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

400

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

403

dccg->funcs->otg_drop_pixel(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

404

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

406

dccg->funcs->set_fifo_errdet_ovr_en(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

407

dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

439

struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

453

dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

455

dccg->funcs->otg_add_pixel(dccg,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

457

dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

33

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

130

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

137

dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1309

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1424

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

1433

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

202

struct dccg *dccg = clk_mgr_internal->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

233

has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

234

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

242

!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

260

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

277

dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

288

dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

301

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

322

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

325

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

326

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

334

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

59

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h

66

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1573

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1589

clk_mgr->dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

531

struct dccg *dccg = clk_mgr->dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

544

use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

553

dccg->ctx->dc->link_srv->dp_get_encoding_format(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

564

clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

585

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

588

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

589

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

111

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1048

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

1058

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

174

clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

195

prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

198

clk_mgr->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

199

clk_mgr->dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

207

clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

839

clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

59

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

419

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c

429

clk_mgr->base.dccg = dccg;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.h

44

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/core/dc.c

1095

dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/core/dc.c

3969

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/core/dc.c

4005

if (dccg && dccg->funcs->set_dto_dscclk &&

drivers/gpu/drm/amd/display/dc/core/dc.c

4010

hwss_add_dccg_set_dto_dscclk(seq_state, dccg, dsc->inst,

drivers/gpu/drm/amd/display/dc/core/dc.c

4021

hwss_add_dccg_set_dto_dscclk(seq_state, dccg, odm_dsc->inst,

drivers/gpu/drm/amd/display/dc/core/dc.c

7494

state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

7501

state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz;

drivers/gpu/drm/amd/display/dc/core/dc.c

7502

state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10;

drivers/gpu/drm/amd/display/dc/core/dc.c

7503

state->dccg.dppclk_enable[i] = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7508

state->dccg.dpstreamclk_enable[i] = 1;

drivers/gpu/drm/amd/display/dc/core/dc.c

7510

state->dccg.dpstreamclk_enable[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7514

state->dccg.dppclk_khz[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7515

state->dccg.pixclk_khz[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7516

state->dccg.dppclk_enable[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7518

state->dccg.dpstreamclk_enable[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7527

state->dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */

drivers/gpu/drm/amd/display/dc/core/dc.c

7529

state->dccg.dscclk_khz[i] = 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7535

state->dccg.symclk32_le_enable[i] = 0; /* Default: disabled */

drivers/gpu/drm/amd/display/dc/core/dc.c

7548

state->dccg.symclk32_le_enable[hpo_le_inst] = 1;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2639

struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2643

if (dccg && dccg->funcs->set_dto_dscclk)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2644

dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3294

struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3302

if (dccg && dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3303

dccg->funcs->set_ref_dscclk(dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3364

struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3368

if (dccg && dccg->funcs->update_dpp_dto)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3369

dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3853

struct dccg *dccg, int inst, int num_slices_h)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3857

seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4373

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4379

seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4497

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4503

seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg;

drivers/gpu/drm/amd/display/dc/dc.h

3259

} dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

102

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

108

void dccg2_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

111

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

120

void dccg2_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

123

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

132

void dccg2_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

134

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

148

void dccg2_refclk_setup(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

150

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

157

bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

159

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

164

void dccg2_allow_clock_gating(struct dccg *dccg, bool allow)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

166

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

177

void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

179

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

197

struct dccg *dccg2_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

204

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

222

void dcn_dccg_destroy(struct dccg **dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

224

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

227

*dccg = NULL;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

32

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

45

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

47

void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

51

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

52

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

74

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

77

void dccg2_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

81

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

99

void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

517

struct dccg base;

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

523

void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

525

void dccg2_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

529

void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

531

void dccg2_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

533

void dccg2_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

537

void dccg2_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

539

void dccg2_refclk_setup(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

540

void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

541

void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

542

bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

544

struct dccg *dccg2_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

550

void dcn_dccg_destroy(struct dccg **dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

32

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

46

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

48

static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

67

struct dccg *dccg201_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c

74

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.h

31

struct dccg *dccg201_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

114

static void dccg21_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

116

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

118

if (dccg2_is_s0i3_golden_init_wa_done(dccg))

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

143

struct dccg *dccg21_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

150

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

31

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

44

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

46

static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

48

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

50

if (dccg->ref_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

51

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

96

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.h

29

struct dccg *dccg21_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

106

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

124

struct dccg *dccg30_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

131

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

30

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

43

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

45

void dccg3_enable_hdmicharclk(struct dccg *dccg, int hpo_inst, int phypll_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

47

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

77

void dccg3_disable_hdmicharclk(struct dccg *dccg, int hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

79

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c

99

struct dccg *dccg3_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

54

struct dccg *dccg3_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

60

struct dccg *dccg30_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

67

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.h

72

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

30

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

31

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

43

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

58

struct dccg *dccg301_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c

65

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h

59

struct dccg *dccg301_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

100

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

124

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

130

static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

132

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

134

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

163

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

170

dccg31_disable_dpstreamclk(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

172

dccg31_enable_dpstreamclk(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

176

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

180

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

187

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

196

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

205

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

214

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

229

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

232

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

240

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

249

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

258

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

267

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

279

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

283

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

306

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

309

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

32

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

33

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

330

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

334

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

336

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

356

void dccg31_disable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

358

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

360

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

400

void dccg31_enable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

402

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

404

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

445

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

45

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

450

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

459

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

466

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

47

void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

476

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

483

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

493

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

500

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

51

if (dccg->dpp_clock_gated[dpp_inst]) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

510

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

517

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

527

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

534

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

547

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

550

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

59

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

60

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

613

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

616

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

644

void dccg31_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

648

(void)dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

658

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

661

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

668

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

673

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

686

static void dccg31_disable_hdmistreamclk(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

688

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

690

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

696

void dccg31_enable_hdmicharclk(struct dccg *dccg, int hpo_inst, int phypll_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

698

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

701

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

735

void dccg31_disable_hdmicharclk(struct dccg *dccg, int hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

737

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

740

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

748

void dccg31_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

754

dccg31_disable_symclk32_se(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

755

dccg31_disable_symclk32_se(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

756

dccg31_disable_symclk32_se(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

757

dccg31_disable_symclk32_se(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

759

dccg31_set_symclk32_le_root_clock_gating(dccg, 0, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

760

dccg31_set_symclk32_le_root_clock_gating(dccg, 1, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

762

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

763

dccg31_disable_dpstreamclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

764

dccg31_disable_dpstreamclk(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

765

dccg31_disable_dpstreamclk(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

766

dccg31_disable_dpstreamclk(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

769

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

770

dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

771

dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

772

dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

773

dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

774

dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

776

dccg31_disable_hdmistreamclk(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

778

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

779

dccg31_disable_hdmicharclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

782

void dccg31_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

785

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

791

void dccg31_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

794

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

800

void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

802

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

81

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

950

struct dccg *dccg31_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

957

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

98

static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

165

struct dccg *dccg31_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

171

void dccg31_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

174

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

179

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

183

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

188

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

192

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

197

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

203

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

206

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

211

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

215

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

220

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

225

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

230

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

236

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

240

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

244

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

248

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

251

void dccg31_disable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

253

void dccg31_enable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

255

void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

102

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

107

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

118

dccg314_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

150

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

154

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

207

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

210

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

232

dccg314_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

251

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

256

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

259

dccg314_set_dtbclk_p_src(dccg, src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

290

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

294

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

297

dccg314_set_dtbclk_p_src(dccg, src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

311

static void dccg314_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

320

dccg31_disable_symclk32_se(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

322

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

324

dccg31_disable_symclk32_le(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

326

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

328

dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

331

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

333

dccg31_set_physymclk(dccg, otg_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

338

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

34

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

349

dccg314_set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

35

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

353

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

357

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

359

if (dccg->dpp_clock_gated[dpp_inst] != clock_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

376

dccg->dpp_clock_gated[dpp_inst] = !clock_on;

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

414

struct dccg *dccg314_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

421

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

47

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

50

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

52

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

60

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

65

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

202

struct dccg *dccg314_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

209

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

102

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

107

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

118

dccg32_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

150

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

154

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

206

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

209

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

231

dccg32_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

249

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

261

dccg32_set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

264

static void dccg32_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

268

(void)dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

278

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

283

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

287

dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

31

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

314

static void dccg32_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

317

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

323

static void dccg32_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

326

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

332

static void dccg32_set_hdmistreamclk(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

336

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

340

dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

354

static void dccg32_enable_hdmicharclk(struct dccg *dccg, int hpo_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

357

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

426

struct dccg *dccg32_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

433

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

44

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

47

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

49

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

60

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

65

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

119

struct dccg *dccg32_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1005

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1009

dccg35_set_symclk_fe_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1010

dccg35_set_symclk_fe_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1014

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1017

dccg35_set_symclk_fe_src_new(dccg, SYMCLK_FE_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1018

dccg35_set_symclk_fe_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1022

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1026

dccg35_set_symclk_be_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1027

dccg35_set_symclk_be_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1031

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1037

dccg35_set_symclk_be_src_new(dccg, inst, SYMCLK_BE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1042

if (dccg35_is_fe_rcg(dccg, i) == 0) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1043

if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1044

dccg35_disable_symclk_fe_new(dccg, i);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1048

dccg35_set_symclk_be_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1052

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1056

dccg35_set_symclk32_se_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1057

dccg35_set_symclk32_se_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1061

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1064

dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1065

dccg35_set_symclk32_se_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1069

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1073

dccg35_set_symclk32_le_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1074

dccg35_set_symclk32_le_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1078

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1084

dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1089

if (dccg35_is_symclk32_se_rcg(dccg, i) == 0) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1091

if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1092

dccg35_disable_symclk32_se_new(dccg, i);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1096

dccg35_set_symclk32_le_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1099

static void dccg35_enable_physymclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1103

dccg35_set_physymclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1104

dccg35_set_physymclk_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1107

static void dccg35_disable_physymclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1110

dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1111

dccg35_set_physymclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1115

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1119

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1125

dccg35_set_dppclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1126

dcn35_set_dppclk_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1135

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1138

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1144

dcn35_set_dppclk_src_new(dccg, inst, DPP_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1148

dccg35_set_dppclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1151

static void dccg35_disable_dscclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1154

dccg35_set_dsc_clk_src_new(dccg, inst, DSC_CLK_REF_CLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1155

dccg35_set_dsc_clk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1158

static void dccg35_enable_dscclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1162

dccg35_set_dsc_clk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1163

dccg35_set_dsc_clk_src_new(dccg, inst, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1166

static void dccg35_enable_dtbclk_p_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1170

dccg35_set_dtbclk_p_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1171

dccg35_set_dtbclk_p_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1174

static void dccg35_disable_dtbclk_p_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1177

dccg35_set_dtbclk_p_src_new(dccg, DTBCLK_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1178

dccg35_set_dtbclk_p_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1181

static void dccg35_disable_dpstreamclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1184

dccg35_set_dpstreamclk_src_new(dccg, DP_STREAM_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1185

dccg35_set_dpstreamclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1188

static void dccg35_enable_dpstreamclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1192

dccg35_set_dpstreamclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1193

dccg35_set_dpstreamclk_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1197

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1200

dccg35_set_hdmistreamclk_src_new(dccg, HDMI_STREAM_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1201

dccg35_set_hdmistreamclk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1204

static void dccg35_enable_hdmistreamclk_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1208

dccg35_set_hdmistreamclk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1209

dccg35_set_hdmistreamclk_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1212

static void dccg35_enable_hdmicharclk_new(struct dccg *dccg, enum hdmi_char_clk src,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1215

dccg35_set_hdmi_char_clk_rcg(dccg, inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1216

dccg35_set_hdmi_char_clk_src_new(dccg, src, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1219

static void dccg35_disable_hdmicharclk_new(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1221

dccg35_set_hdmi_char_clk_src_new(dccg, HDMI_CHAR_REFCLK, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1222

dccg35_set_hdmi_char_clk_rcg(dccg, inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1225

void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1227

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1236

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1238

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1246

static void dcn35_set_dppclk_enable(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1249

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1272

void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1274

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1276

if (dccg->dpp_clock_gated[dpp_inst]) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1283

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1284

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1295

dccg35_set_dppclk_rcg(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1301

dcn35_set_dppclk_enable(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1303

dcn35_set_dppclk_enable(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1304

dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1307

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1310

static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1313

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1315

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1342

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1347

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

138

static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1384

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1389

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

140

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1401

dccg35_get_pixel_rate_div(dccg, otg_inst, &cur_k1, &cur_k2);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

142

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1431

dccg35_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1435

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1439

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1491

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1494

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1531

dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1574

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1579

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1582

dccg35_set_dtbclk_p_src(dccg, src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1589

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1595

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1601

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1607

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1618

void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1620

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1624

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1630

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1636

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1642

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1658

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1662

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1665

dccg35_set_dtbclk_p_src(dccg, src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1679

void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1681

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1683

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1689

static void dccg35_enable_hdmicharclk(struct dccg *dccg, int hpo_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

169

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1692

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1694

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

173

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1740

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1744

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1746

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

175

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1779

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1784

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1852

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1864

dccg35_set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1867

void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1869

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1871

if (dccg->dpp_clock_gated[dpp_inst] != clock_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1875

dccg35_set_dppclk_rcg(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1878

dcn35_set_dppclk_enable(dccg, dpp_inst, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1883

dcn35_set_dppclk_enable(dccg, dpp_inst, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1889

dccg35_set_dppclk_rcg(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1895

dccg->dpp_clock_gated[dpp_inst] = !clock_on;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1899

void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1901

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1909

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1920

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1931

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1942

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1956

static void dccg35_disable_hdmistreamclk(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1958

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1960

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1969

static void dccg35_disable_hdmicharclk(struct dccg *dccg, int hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1971

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1974

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1983

static void dccg35_init_cb(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1985

(void)dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1988

void dccg35_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1996

dccg35_disable_symclk32_se(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1998

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2000

dccg31_disable_symclk32_le(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2001

dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2011

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2013

dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2015

dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2020

dccg35_disable_hdmistreamclk(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2021

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2022

dccg35_disable_hdmicharclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2029

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2031

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2036

void dccg35_enable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2038

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

208

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2083

void dccg35_disable_dscclk(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2085

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2093

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2101

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2109

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2117

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

212

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2128

void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2130

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2136

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

214

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2142

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2148

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2154

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2160

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2170

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2177

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2184

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2191

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2198

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2205

static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2209

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2235

void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2238

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2279

num_enabled_symclk_fe = dccg35_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2318

static void dccg35_enable_hdmicharclk_cb(struct dccg *dccg, int hpo_inst, int phypll_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2327

dccg35_enable_hdmicharclk_new(dccg, src, hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2330

dccg35_set_physymclk_src_new(dccg, phypll_inst, PHYSYMCLK_PHYD18CLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2333

static void dccg35_disable_hdmicharclk_cb(struct dccg *dccg, int hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2340

dccg35_disable_hdmicharclk_new(dccg, hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2346

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

235

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2373

dccg35_disable_dtbclk_p_new(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2374

dccg35_disable_hdmistreamclk_new(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2376

dccg35_enable_dtbclk_p_new(dccg, dtb_clk_src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2377

dccg35_enable_hdmistreamclk_new(dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2384

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

239

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2394

dccg35_enable_hdmicharclk_new(dccg, HDMI_CHAR_REFCLK, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2395

dccg35_enable_hdmistreamclk_new(dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2399

dccg35_disable_hdmistreamclk_new(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2400

dccg35_disable_hdmicharclk_new(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2405

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

241

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2434

dccg35_disable_dtbclk_p_new(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2435

dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2437

dccg35_enable_dtbclk_p_new(dccg, dtb_clk_src, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2438

dccg35_enable_dpstreamclk_new(dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2445

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2456

dccg35_enable_dpstreamclk_new(dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2460

dccg35_disable_dpstreamclk_new(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2463

static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2466

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2468

if (dccg->dpp_clock_gated[dpp_inst]) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2475

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2476

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2489

dccg35_enable_dpp_clk_new(dccg, dpp_inst, DPP_DCCG_DTO);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2496

dccg35_disable_dpp_clk_new(dccg, dpp_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2498

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2502

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2506

if (dccg->dpp_clock_gated[dpp_inst] == power_on)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2513

dccg35_set_dppclk_rcg(dccg, dpp_inst, !power_on);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2515

dccg->dpp_clock_gated[dpp_inst] = !power_on;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2519

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2523

dccg35_enable_symclk32_se_new(dccg, inst, (enum symclk32_se_clk_source)phyd32clk);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2526

static void dccg35_disable_symclk32_se_cb(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2528

dccg35_disable_symclk32_se_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2532

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2536

dccg35_enable_symclk32_le_new(dccg, inst, (enum symclk32_le_clk_source) src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2539

static void dccg35_disable_symclk32_le_cb(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2541

dccg35_disable_symclk32_le_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2545

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2555

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2557

dccg35_disable_symclk32_le_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2561

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2568

dccg35_enable_physymclk_new(dccg, inst, (enum physymclk_source)clk_src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2570

dccg35_disable_physymclk_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2574

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2582

dccg35_enable_physymclk_new(dccg, inst, PHYSYMCLK_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2584

dccg35_disable_physymclk_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2588

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2598

dccg35_enable_symclk32_le_new(dccg, inst, SYMCLK32_LE_REFCLK);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2600

dccg35_disable_symclk32_le_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2604

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2609

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2611

dccg35_disable_dtbclk_p_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2615

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2621

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2628

dccg35_enable_dtbclk_p_new(dccg, DTBCLK_DTBCLK0, params->otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2645

dccg35_set_pixel_rate_div(dccg, params->otg_inst, PIXEL_RATE_DIV_BY_1, PIXEL_RATE_DIV_BY_1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2654

dccg35_disable_dtbclk_p_new(dccg, params->otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2665

static void dccg35_disable_dscclk_cb(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2668

dccg35_disable_dscclk_new(dccg, inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2671

static void dccg35_enable_dscclk_cb(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2673

dccg35_enable_dscclk_new(dccg, inst, DSC_DTO_TUNED_CK_GPU_DISCLK_3);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2676

static void dccg35_enable_symclk_se_cb(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2679

dccg35_enable_symclk_be_new(dccg, SYMCLK_BE_PHYCLK, link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2681

dccg35_enable_symclk_fe_new(dccg, stream_enc_inst, (enum symclk_fe_source) link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2686

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2691

dccg35_disable_symclk_fe_new(dccg, stream_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2696

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2698

dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

272

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

276

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

278

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2781

struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2788

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

31

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

319

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

32

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

324

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

327

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

367

static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

370

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

372

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

394

static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

396

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

398

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

425

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

429

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

431

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

45

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

462

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

466

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

468

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

499

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

503

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

505

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

520

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

524

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

527

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

542

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

546

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

565

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

569

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

584

static void dccg35_set_dsc_clk_src_new(struct dccg *dccg, int inst, enum dsc_clk_source src)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

586

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

610

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

615

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

645

dccg35_is_symclk32_se_src_functional_le_new(struct dccg *dccg, int symclk_32_se_inst, int symclk_32_le_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

651

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

663

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

667

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

686

static void dcn35_set_dppclk_src_new(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

689

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

711

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

715

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

749

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

753

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

789

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

793

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

833

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

837

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

868

static int dccg35_is_symclk_fe_src_functional_be(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

876

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

902

static void dccg35_set_symclk_fe_src_new(struct dccg *dccg, enum symclk_fe_source src, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

904

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

935

static uint32_t dccg35_is_fe_rcg(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

938

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

968

static uint32_t dccg35_is_symclk32_se_rcg(struct dccg *dccg, int inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

972

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

244

struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

250

void dccg35_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

252

void dccg35_trigger_dio_fifo_resync(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

254

void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

256

void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

257

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

259

void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

261

void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

263

void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

265

void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

267

void dccg35_enable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

268

void dccg35_disable_dscclk(struct dccg *dccg, int inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

270

void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

271

void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

100

dcn401_set_dppclk_enable(dccg, dpp_inst, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

103

dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

110

struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

112

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

121

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

126

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

159

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

165

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

175

dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

187

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

193

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

199

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

205

dccg401_wait_for_dentist_change_done(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

215

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

219

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

270

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

275

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

284

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

291

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

301

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

308

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

318

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

325

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

335

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

342

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

353

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

357

(void)dccg;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

366

static void dccg401_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

369

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

375

static void dccg401_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

378

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

385

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

389

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

401

void dccg401_enable_hdmicharclk(struct dccg *dccg, int hpo_inst, int phypll_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

403

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

406

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

41

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

418

dccg401_set_physymclk(dccg, phypll_inst, PHYSYMCLK_FORCE_SRC_PHYD18CLK, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

42

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

421

void dccg401_disable_hdmicharclk(struct dccg *dccg, int hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

423

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

434

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

442

static void dccg401_disable_hdmistreamclk(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

444

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

451

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

455

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

460

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

469

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

478

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

487

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

502

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

505

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

513

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

522

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

531

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

54

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

540

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

551

static void dccg401_enable_dpstreamclk(struct dccg *dccg, int otg_inst, int dp_hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

553

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

558

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

56

static void dcn401_set_dppclk_enable(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

567

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

576

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

585

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

59

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

599

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

601

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

607

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

615

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

623

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

631

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

643

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

650

dccg401_disable_dpstreamclk(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

652

dccg401_enable_dpstreamclk(dccg, otg_inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

656

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

659

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

725

dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

759

void dccg401_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

765

dccg31_disable_symclk32_se(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

766

dccg31_disable_symclk32_se(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

767

dccg31_disable_symclk32_se(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

768

dccg31_disable_symclk32_se(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

770

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

771

dccg401_disable_symclk32_le(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

772

dccg401_disable_symclk32_le(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

773

dccg401_disable_symclk32_le(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

774

dccg401_disable_symclk32_le(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

777

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

778

dccg401_disable_dpstreamclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

779

dccg401_disable_dpstreamclk(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

78

void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

780

dccg401_disable_dpstreamclk(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

781

dccg401_disable_dpstreamclk(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

784

if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

785

dccg401_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

786

dccg401_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

787

dccg401_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

788

dccg401_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

790

dccg401_disable_hdmistreamclk(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

792

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

793

dccg401_disable_hdmicharclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

796

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

799

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

80

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

82

if (dccg->ref_dppclk && req_dppclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

83

int ref_dppclk = dccg->ref_dppclk;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

833

void dccg401_set_ref_dscclk(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

836

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

868

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

870

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

877

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

884

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

891

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

898

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

914

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

917

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

98

dcn401_set_dppclk_enable(dccg, dpp_inst, true);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

984

struct dccg *dccg401_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

991

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

193

void dccg401_init(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

195

void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

196

void dccg401_get_dccg_ref_freq(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

200

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

205

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

209

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

211

void dccg401_disable_dpstreamclk(struct dccg *dccg, int dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

212

void dccg401_set_dto_dscclk(struct dccg *dccg, uint32_t inst, uint32_t num_slices_h);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

213

void dccg401_set_ref_dscclk(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

216

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

219

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

224

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

229

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

231

void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

232

void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

234

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

237

struct dccg *dccg401_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

244

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

249

void dccg401_set_hdmistreamclk(struct dccg *dccg, enum streamclk_source src, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

250

void dccg401_enable_hdmicharclk(struct dccg *dccg, int hpo_inst, int phypll_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

251

void dccg401_disable_hdmicharclk(struct dccg *dccg, int hpo_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

11

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

111

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

12

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

127

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

143

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

159

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

175

dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

184

static void dccg42_disable_hdmistreamclk(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

186

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

194

dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

197

static void dccg42_disable_hdmicharclk(struct dccg *dccg, int hpo_inst)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

199

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

207

HDMICHARCLK0_ROOT_GATE_DISABLE, dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

211

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

217

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

227

dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

24

dccg->ctx->logger

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

257

void dccg42_trigger_dio_fifo_resync(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

259

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

26

void dccg42_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

266

static void dccg42_init(struct dccg *dccg)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

269

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

276

dccg35_disable_symclk32_se(dccg, otg_inst);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

278

if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

279

dccg401_disable_symclk32_le(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

280

dccg401_disable_symclk32_le(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

281

dccg401_disable_symclk32_le(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

282

dccg401_disable_symclk32_le(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

285

if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

286

dccg401_disable_dpstreamclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

287

dccg401_disable_dpstreamclk(dccg, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

288

dccg401_disable_dpstreamclk(dccg, 2);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

289

dccg401_disable_dpstreamclk(dccg, 3);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

29

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

291

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) {

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

299

dccg42_disable_hdmistreamclk(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

300

if (dccg->ctx->dc->debug.root_clock_optimization.bits.hdmichar)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

301

dccg42_disable_hdmicharclk(dccg, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

346

struct dccg *dccg42_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

353

struct dccg *base;

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

53

void dccg42_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

56

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

80

void dccg42_enable_global_fgcg(struct dccg *dccg, bool value)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

82

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

84

if (dccg->ctx->dc->debug.disable_clock_gate)

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

90

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

95

struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

244

void dccg42_otg_add_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

247

void dccg42_otg_drop_pixel(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

249

void dccg42_enable_global_fgcg(struct dccg *dccg, bool value);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

252

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

258

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

263

void dccg42_trigger_dio_fifo_resync(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h

265

struct dccg *dccg42_create(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1115

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1116

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1122

clock_source->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1123

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1132

clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto(

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1133

clock_source->ctx->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1207

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1238

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1242

if (dccg) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1243

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1244

dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1246

if (dccg && dccg->funcs->set_dtbclk_dto)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1247

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1250

} else if (dccg && dccg->funcs->disable_symclk_se) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1252

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1327

if (link->dc->res_pool->dccg &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1328

link->dc->res_pool->dccg->funcs->set_hdmistreamclk) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1329

link->dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1330

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1959

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1988

if (dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1989

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2094

dc->res_pool->dccg->funcs->get_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2095

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2537

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2545

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2546

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2550

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2551

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2590

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2598

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2599

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2603

dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

2604

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3080

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3083

if (dccg)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3084

dccg->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3085

dccg,

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3094

struct clk_mgr *dccg = dc->clk_mgr;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3098

if (dccg)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3099

dccg->funcs->update_clocks(

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3100

dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1827

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1828

dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1841

if (res_pool->dccg && res_pool->hubbub) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1843

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1935

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1936

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3084

if (dc->res_pool->dccg)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3085

dc->res_pool->dccg->funcs->update_dpp_dto(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3086

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1684

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1692

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2214

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2237

if (dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2238

dccg->funcs->set_ref_dscclk(dccg, dsc->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2832

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2894

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2898

if (dccg && dccg->funcs->set_dtbclk_dto)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2899

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3047

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3063

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3065

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3069

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3071

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3074

if (dccg->funcs->enable_symclk_se

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3080

if (dccg->funcs->disable_symclk_se)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3081

dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3084

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3089

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3090

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3091

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3160

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3161

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3176

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3177

dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

363

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

364

dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

841

if (dc->res_pool->dccg->funcs->set_pixel_rate_div)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

842

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

843

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

884

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

888

if (dccg->funcs->set_dtbclk_p_src)

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

889

dccg->funcs->set_dtbclk_p_src(dccg, DTBCLK0, tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

896

dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

234

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

235

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

247

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

370

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

371

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

91

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

92

return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1308

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1334

if (dccg)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1335

if (dccg->funcs->dccg_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1336

dccg->funcs->dccg_read_reg_state(dccg, out_data->dccg_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

58

#define TO_DCN_DCCG(dccg)\

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

59

container_of(dccg, struct dcn_dccg, base)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

659

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

660

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

691

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

807

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

808

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

947

(!dc->res_pool->dccg->funcs->enable_hdmicharclk))

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

132

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

133

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

143

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

252

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

253

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

294

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

296

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

297

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

337

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

338

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

339

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

236

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

238

hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

239

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

290

if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

291

hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

292

hws->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

428

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

463

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

464

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

465

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1033

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1043

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1082

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1092

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1286

hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

805

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

806

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

829

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

971

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

972

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1376

if (dc->res_pool->dccg->funcs->enable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1377

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1379

if (dc->res_pool->dccg->funcs->disable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1380

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

165

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

166

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

176

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

291

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

292

dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

493

if (hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

494

hws->ctx->dc->res_pool->dccg->funcs->dpp_root_clock_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

495

hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

504

if (hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

505

hws->ctx->dc->res_pool->dccg->funcs->set_dpstreamclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

506

hws->ctx->dc->res_pool->dccg, dp_hpo_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

515

if (hws->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

516

hws->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

517

hws->ctx->dc->res_pool->dccg, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

526

if (hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

527

hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating(

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

528

hws->ctx->dc->res_pool->dccg, phy_inst, clock_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1004

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1020

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1022

dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1024

dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1027

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1034

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1035

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1036

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

163

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

164

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1722

bool should_use_dto_dscclk = (dc->res_pool->dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1733

hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1751

hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

187

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2116

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2117

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3590

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3617

if (dccg && dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3618

hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

362

if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

363

dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3700

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3713

hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

829

if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

830

dc->res_pool->dccg->funcs->set_pixel_rate_div(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

831

dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

847

if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

849

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

851

dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DTBCLK0, pipe_ctx->stream_res.tg->inst);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

107

(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1435

if (dc->res_pool->dccg->funcs->enable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1436

dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1438

if (dc->res_pool->dccg->funcs->disable_dsc)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1439

dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

83

if (res_pool->dccg->funcs->dccg_init)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

84

res_pool->dccg->funcs->dccg_init(res_pool->dccg);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2042

struct dccg *dccg, int inst, int num_slices_h);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2185

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2231

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

249

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

653

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

659

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

324

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

426

struct dccg;

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

428

struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h

445

struct dccg *dccg;

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

214

void (*update_dpp_dto)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

217

void (*get_dccg_ref_freq)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

220

void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

222

void (*otg_add_pixel)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

224

void (*otg_drop_pixel)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

226

void (*dccg_init)(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

227

void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

228

void (*allow_clock_gating)(struct dccg *dccg, bool allow);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

229

void (*enable_memory_low_power)(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

230

bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

231

void (*enable_hdmicharclk)(struct dccg *dccg, int hpo_inst, int phypll_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

232

void (*disable_hdmicharclk)(struct dccg *dccg, int hpo_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

234

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

239

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

242

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

247

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

253

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

258

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

262

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

267

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

271

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

276

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

282

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

287

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

291

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

295

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

299

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

303

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

306

void (*set_pixel_rate_div)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

311

void (*get_pixel_rate_div)(struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

317

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

323

struct dccg *dccg);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

326

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

331

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

336

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

340

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

343

struct dccg *dccg,

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

346

void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

347

void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

348

void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

349

void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

350

void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable);

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

120

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

121

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

122

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

144

if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating)

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

145

link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating(

drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c

146

link->dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1940

(!core_dc->res_pool->dccg->funcs->enable_hdmicharclk) ||

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1993

if (core_dc->res_pool->dccg->funcs->set_valid_pixel_rate)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1994

core_dc->res_pool->dccg->funcs->set_valid_pixel_rate(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

1995

core_dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2012

if (core_dc->res_pool->dccg->funcs->set_hdmistreamclk) {

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2013

core_dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

2014

core_dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

726

struct dccg *dccg = dc->res_pool->dccg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

736

bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) &&

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

761

dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

768

dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

866

if (dccg->funcs->set_ref_dscclk)

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

867

dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst);

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1016

if (dc->res_pool->dccg->funcs->set_hdmistreamclk) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1017

dc->res_pool->dccg->funcs->set_hdmistreamclk(

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

1018

dc->res_pool->dccg,

drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c

957

(!link_stream->ctx->dc->res_pool->dccg->funcs->enable_hdmicharclk) ||

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

127

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

128

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

134

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) {

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

136

pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

137

pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

200

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

201

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

231

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

232

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

286

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

287

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

293

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

294

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

490

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

491

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

498

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

499

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

60

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

61

pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc(

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

62

pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

85

if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg)

drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c

86

pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1219

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1220

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2583

pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2584

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1011

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1012

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1224

pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1225

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1554

pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1555

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

788

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

789

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1345

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1346

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2599

pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2600

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1191

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1192

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1586

pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1587

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1248

if (pool->dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1249

dcn_dccg_destroy(&pool->dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1492

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1493

if (pool->dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1192

if (pool->dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1193

dcn_dccg_destroy(&pool->dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1424

pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1425

if (pool->dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1648

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1649

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2215

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2216

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1707

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1708

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2134

pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2135

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1650

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1651

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2167

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2168

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1640

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1641

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2039

pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

2040

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1657

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1658

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2526

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2527

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1631

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1632

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2019

pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

2020

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1712

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1713

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2172

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2173

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1692

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1693

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2144

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2145

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1699

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1700

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2142

pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2143

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1647

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1648

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2229

pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2230

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1645

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1646

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2217

pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2218

if (pool->base.dccg == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1610

if (pool->base.dccg != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1611

dcn_dccg_destroy(&pool->base.dccg);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2169

pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2170

if (pool->base.dccg == NULL) {