drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3130

struct dc_dwb_params *dwb_params = params->dwbc_enable_params.dwb_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3147

struct dc_dwb_params *dwb_params = params->dwbc_update_params.dwb_params;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4104

struct dc_dwb_params *dwb_params)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4188

struct dc_dwb_params *dwb_params)

drivers/gpu/drm/amd/display/dc/dc_stream.h

71

struct dc_dwb_params dwb_params;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

65

static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

158

static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

250

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

72

void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

99

static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

413

struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

415

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

156

bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

229

void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

67

void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

92

bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

884

bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

888

bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

901

struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

903

void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

907

const struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

911

const struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

357

const struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

390

const struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2095

struct dc_dwb_params *dwb_params);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2123

struct dc_dwb_params *dwb_params);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

535

struct dc_dwb_params *dwb_params;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

544

struct dc_dwb_params *dwb_params;

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

172

struct dc_dwb_params params;

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

182

struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

188

struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

199

struct dc_dwb_params *params);