d4
(_r)->d4 = _interp_map_addr; \
pr_reg[3] = regs->d4; \
int d4, int d5, unsigned long __user *mem);
long d1,d2,d3,d4,d5,d6,d7;
long d4;
DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
.child_tid = (int __user *)regs->d4,
regs->d4);
[3] = PT_REG(d4),
err |= __get_user(regs->d4, &gregs[4]);
err |= __put_user(regs->d4, &gregs[4]);
sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
regs->d4, regs->d5, regs->a0, regs->a1);
u32 d4;
memcpy(&d4, buf, 4);
if (__put_user(d4, target))
u32 d4;
if (__get_user(d4, s))
memcpy(buf, &d4, 4);
be64_to_cpua(83, 7b, 12, e6, b6, 5b, cb, d4),
be64_to_cpua(01, 48, fb, 5f, 72, 2a, d4, 8f),
be64_to_cpua(dd, 3f, 07, 87, 12, a0, d4, ac),
be64_to_cpua(f7, d4, ad, 8d, 94, 5a, 69, 89),
be64_to_cpua(cf, d4, e7, b7, f0, 82, 56, 41),
be64_to_cpua(fb, 9d, 8b, de, d4, 8d, 6f, ad),
be64_to_cpua(f8, 00, dd, ab, d4, c0, 2b, e6),
#define ACPI_INIT_UUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7)
#define CPER_GUID__INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
u32 d1 = 2, d3 = 5, d4 = 0, d5 = 0;
d4 = d8 * 2;
p.pll_reg3.val = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) + (m2div_int << 5));
u8 d4, ipcr; /* Input port change register of block */
u8 d4, acr; /* Auxiliary control register of block */
#define DIVS_INV(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9) \
DIV_INV(d4), DIV_INV(d5), DIV_INV(d6), DIV_INV(d7), \
le32_to_cpu(ev->d3) * le32_to_cpu(ev->d4) * 2;
le32_to_cpu(ev->d3) * le32_to_cpu(ev->d4);
__le32 d4;
__le32 d4;
le16_encode_bits(le16_get_bits(phy_data->d4,
le16_encode_bits(le16_get_bits(phy_data->d4,
le16_encode_bits(le16_get_bits(phy_data->d4,
phy_data.d4 = desc->phy_data4;
__le16 d4;
u16 phy_data4 = le16_to_cpu(phy_data->d4);
#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
snic_trace(char *fn, u16 hno, u32 tag, u64 d1, u64 d2, u64 d3, u64 d4, u64 d5)
tr_rec->data[3] = d4;
#define SNIC_TRC(_hno, _tag, d1, d2, d3, d4, d5) \
(u64)(d4), \
#define SNIC_TRC(_hno, _tag, d1, d2, d3, d4, d5) \
(u64)(d4), \
#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
#define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
u64 d4 = d419 * 2;
u128 s0 = ((((((u128)(r0) * (r0))) + (((u128)(d4) * (r1))))) +
u128 s1 = ((((((u128)(d0) * (r1))) + (((u128)(d4) * (r2))))) +
(((u128)(d4) * (r3))));
d4 += c;
c = (u32)(d4 >> 26);
h4 = (u32)d4 & 0x3ffffff;
u64 d0, d1, d2, d3, d4;
d4 = ((u64)h0 * r4) + ((u64)h1 * r3) +
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 = p1[4];
d4 ^= p2[4];
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 ^= p3[4];
d4 ^= p4[4];
p1[4] = d4;
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 = p1[4];
d4 ^= p2[4];
d4 ^= p3[4];
d4 ^= p4[4];
d4 ^= p5[4];
d4 = p1[4];
p1[4] = d4;
d4 ^= p2[4];
p1[4] = d4;
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 = p1[4];
d4 ^= p2[4];
d4 ^= p3[4];
p1[4] = d4;
d4 = p1[4];
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 ^= p2[4];
d4 ^= p3[4];
d4 ^= p4[4];
p1[4] = d4;
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 = p1[4];
d4 = p1[4];
d4 ^= p2[4];
d4 ^= p3[4];
d4 ^= p4[4];
d4 ^= p5[4];
p1[4] = d4;
d4 ^= p2[4];
p1[4] = d4;
register long d0, d1, d2, d3, d4, d5, d6, d7;
d4 = p1[4];
d4 ^= p2[4];
d4 ^= p3[4];
p1[4] = d4;
register long d0, d1, d2, d3, d4, d5, d6, d7;
struct sockaddr_in *d4 = (struct sockaddr_in *)dst;
d4->sin_addr = is_outer ? param_ipaddr4_outer_dst :
d4->sin_port = htons(UDP_DST_PORT);