ddbwritel
ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM,
ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM,
ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON,
ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr));
ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE,
ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address,
ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
ddbwritel(ci->port->dev, CI_READ_CMD | address,
ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address,
ddbwritel(ci->port->dev, CI_POWER_ON,
ddbwritel(dev, mem & 0xffffffff, dma->bufregs + i * 8);
ddbwritel(dev, mem >> 32, dma->bufregs + i * 8 + 4);
ddbwritel(dev, mem & 0xffffffff, base + i * 8);
ddbwritel(dev, mem >> 32, base + i * 8 + 4);
ddbwritel(dev, I2C_SPEED_400,
ddbwritel(dev, I2C_SPEED_400,
ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
ddbwritel(output->port->dev,
ddbwritel(input->port->dev,
ddbwritel(dev, (dma->cbuf << 11),
ddbwritel(io->port->dev, 0, DMA_BUFFER_ACK(dma));
ddbwritel(dev, s, INTERRUPT_ACK);
ddbwritel(dev, s, INTERRUPT_ACK);
ddbwritel(dev, s, INTERRUPT_ACK);
ddbwritel(dev, 1, tag | SPI_CONTROL);
ddbwritel(dev, data, tag | SPI_DATA);
ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00),
ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00),
ddbwritel(dev, data, tag | SPI_DATA);
ddbwritel(dev, 0, tag | SPI_CONTROL);
ddbwritel(dev, 1, tag | SPI_CONTROL);
ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00),
ddbwritel(dev, 0xffffffff, tag | SPI_DATA);
ddbwritel(dev, 0, tag | SPI_CONTROL);
ddbwritel(dev, 1, GPIO_DIRECTION);
ddbwritel(dev, val & 1, GPIO_OUTPUT);
ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL);
ddbwritel(dev, info->board_control_2,
ddbwritel(dev,
ddbwritel(dev, 1, GPIO_DIRECTION);
ddbwritel(dev, 1, GPIO_OUTPUT);
ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma));
ddbwritel(dev, 0, TS_CONTROL(output));
ddbwritel(dev, 2, TS_CONTROL(output));
ddbwritel(dev, 0, TS_CONTROL(output));
ddbwritel(dev, con, TS_CONTROL(output));
ddbwritel(dev, con2, TS_CONTROL2(output));
ddbwritel(dev, output->dma->bufval,
ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma));
ddbwritel(dev, 1, DMA_BASE_READ);
ddbwritel(dev, 7, DMA_BUFFER_CONTROL(output->dma));
ddbwritel(dev, con | 1, TS_CONTROL(output));
ddbwritel(dev, 0, TS_CONTROL(output));
ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma));
ddbwritel(dev, 0, tag | TS_CONTROL(input));
ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma));
ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma));
ddbwritel(dev, 0, TS_CONTROL(input));
ddbwritel(dev, 2, TS_CONTROL(input));
ddbwritel(dev, 0, TS_CONTROL(input));
ddbwritel(dev, input->dma->bufval,
ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma));
ddbwritel(dev, 1, DMA_BASE_WRITE);
ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma));
ddbwritel(dev, 0x09, TS_CONTROL(input));
ddbwritel(dev, 0x000fff01, TS_CONTROL2(input));
ddbwritel(dev,
ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma));
ddbwritel(dev,
ddbwritel(dev, msg[0].len | (msg[1].len << 16),
ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING);
ddbwritel(dev, ((i2c->rbuf & 0xffff) << 16) | (i2c->wbuf & 0xffff),
ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND);
ddbwritel(dev, istat & 1, INTERRUPT_ACK);
ddbwritel(dev, msg[0].len << 16,
ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH);
ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE);
ddbwritel(dev, 0x00000000, MSI1_ENABLE);
ddbwritel(dev, 0x00000000, MSI2_ENABLE);
ddbwritel(dev, 0x00000000, MSI3_ENABLE);
ddbwritel(dev, 0x00000000, MSI4_ENABLE);
ddbwritel(dev, 0x00000000, MSI5_ENABLE);
ddbwritel(dev, 0x00000000, MSI6_ENABLE);
ddbwritel(dev, 0x00000000, MSI7_ENABLE);
ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE);
ddbwritel(dev, 0x0000000f, MSI1_ENABLE);
ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE);
ddbwritel(dev, 0x00000000, MSI1_ENABLE);
ddbwritel(dev, 0, DMA_BASE_READ);
ddbwritel(dev, 0, DMA_BASE_WRITE);
ddbwritel(dev, 0, INTERRUPT_ENABLE);
ddbwritel(dev, 0, MSI1_ENABLE);
ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(input));
ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb));
ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(dvb->input));
ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(dvb->input));
ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(input));