Symbol: dd_emit
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1000
dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1001
dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1002
dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1003
dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1004
dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1005
dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1006
dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1007
dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1008
dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1009
dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1010
dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1012
dd_emit(ctx, 1, 0); /* ffffffff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1013
dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1014
dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1015
dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1016
dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1017
dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1019
dd_emit(ctx, 8, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1021
dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1022
dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1023
dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1024
dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1026
dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1027
dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1028
dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1029
dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1030
dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1032
dd_emit(ctx, 1, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1033
dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1035
dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1036
dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1038
dd_emit(ctx, 1, 0); /* 00000003 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1039
dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1040
dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1041
dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1042
dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1043
dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1045
dd_emit(ctx, 1, 0xe00); /* 7fff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1046
dd_emit(ctx, 1, 0x1000); /* 7fff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1047
dd_emit(ctx, 1, 0x1e00); /* 7fff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1049
dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1050
dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1051
dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1052
dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1053
dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1054
dd_emit(ctx, 1, 1); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1055
dd_emit(ctx, 1, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1056
dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1057
dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1058
dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1060
dd_emit(ctx, 1, 0x200);
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1061
dd_emit(ctx, 1, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1063
dd_emit(ctx, 1, 1); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1064
dd_emit(ctx, 1, 0x70); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1065
dd_emit(ctx, 1, 0x80); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1066
dd_emit(ctx, 1, 0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1067
dd_emit(ctx, 1, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1068
dd_emit(ctx, 1, 1); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1069
dd_emit(ctx, 1, 0x70); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1070
dd_emit(ctx, 1, 0x80); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1071
dd_emit(ctx, 1, 0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1073
dd_emit(ctx, 1, 1); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1074
dd_emit(ctx, 1, 0xf0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1075
dd_emit(ctx, 1, 0xff); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1076
dd_emit(ctx, 1, 0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1077
dd_emit(ctx, 1, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1078
dd_emit(ctx, 1, 1); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1079
dd_emit(ctx, 1, 0xf0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1080
dd_emit(ctx, 1, 0xff); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1081
dd_emit(ctx, 1, 0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1082
dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1086
dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1087
dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1088
dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1089
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1090
dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1091
dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1092
dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1093
dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1094
dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1095
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1096
dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1097
dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1098
dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1099
dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1100
dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1101
dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1102
dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1103
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1104
dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
1105
dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
802
dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
803
dd_emit(ctx, 1, 0); /* 00000001 UNK135C */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
806
dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
807
dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
808
dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
809
dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
810
dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
812
dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
813
dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
814
dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
817
dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
818
dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
819
dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
820
dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
821
dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
822
dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
823
dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
824
dd_emit(ctx, 1, 1); /* 00000001 LANES32 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
825
dd_emit(ctx, 1, 0); /* 000000ff UNK370 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
826
dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
827
dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
828
dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
829
dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
830
dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
831
dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
832
dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
833
dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
834
dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
835
dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
836
dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
837
dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
838
dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
839
dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
841
dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
842
dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
843
dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
844
dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
845
dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
846
dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
847
dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
848
dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
849
dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
853
dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
855
dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
857
dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
858
dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
859
dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
861
dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
862
dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
863
dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
864
dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
865
dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
866
dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
867
dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
868
dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
869
dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
870
dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
872
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
873
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
874
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
875
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
876
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
877
dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
878
dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
879
dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
880
dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
881
dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
883
dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
884
dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
886
dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
888
dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
889
dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
890
dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
891
dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
895
dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
896
dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
897
dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
898
dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
899
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
900
dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
901
dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
902
dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
903
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
904
dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
905
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
906
dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
907
dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
908
dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
909
dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
913
dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
914
dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
916
dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
917
dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
919
dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
920
dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
921
dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
922
dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
923
dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
924
dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
925
dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
926
dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
927
dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
928
dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
929
dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
930
dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
932
dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
936
dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
937
dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
938
dd_emit(ctx, 1, 0); /* 000000ff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
939
dd_emit(ctx, 1, 0); /* ffffffff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
940
dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
941
dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
942
dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
943
dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
944
dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
945
dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
947
dd_emit(ctx, 1, 0); /* ffffffff */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
948
dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
950
dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
952
dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
954
dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
955
dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
956
dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
958
dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
959
dd_emit(ctx, 1, 0); /* 00000001 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
961
dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
962
dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
963
dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
964
dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
965
dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
966
dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
967
dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
968
dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
970
dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
971
dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
972
dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
973
dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
974
dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
975
dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
976
dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
977
dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
978
dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
979
dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
980
dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
981
dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
982
dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
984
dd_emit(ctx, 3, 0); /* 1, 1, 1 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
986
dd_emit(ctx, 2, 0); /* 1, 1 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
987
dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
988
dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
989
dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
990
dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
992
dd_emit(ctx, 1, 3); /* 00000003 */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
993
dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
996
dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
997
dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
998
dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */